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CHAPTER 21 MULTI-PULSE GENERATOR
21.2 Block Diagram
● 16-bit MPG output control register (upper) (OPCUR) and 16-bit MPG output control register
(lower) (OPCLR)
The 16-bit MPG output control register (upper) (OPCUR) and the 16-bit MPG output control
register (lower) (OPCLR) are registers that enable the write timing interrupt and flag, position
detect interrupt and flag, set the data transfer method, and control the output of the OPT5 to
OPT0 pins and the input of the DTTI pin.
● 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx)
The output data buffer register is composed of 12 pairs of registers (OPDBRHB and
OPDBRLB to OPDBRH0 and OPDBRL0). OPDBRHx is the upper byte register and
OPDBRLx the lower byte register. When a write signal is generated in the data write control
circuit, the values of the OPDBRHx register and OPDBRLx register specified by the BNKF bit
and the RDA[2:0] bits are transferred to the 16-bit MPG output data register (upper) (OPDUR)
and the 16-bit MPG output data register (lower) (OPDLR). However, when the value of the
OPS[2:0] bits are "0b000", regardless of the settings of the BNKF bit and RDA[2:0] bits, the
values of the OPDBRHx register and OPDBRLx register are always output to the OPDUR
register and OPDLR register.
● 16-bit MPG output data register (upper) (OPDUR) and 16-bit MPG output data register
(lower) (OPDLR)
The 16-bit MPG output data register (upper) (OPDUR) and the 16-bit MPG output data register
(lower) (OPDLR) are used to store the output data to the OPT5 to OPT0 pins.
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FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-1v0-E
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