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MB95630H Series
■ 16-bit Timer Timing
The 16-bit timer increases its value at timing according to the prescaler clock and counts up at
a rising edge.
Note:
Before the prescaler clock is changed, the Timer Counter should be disabled first by
setting the TMEN bit to "0".
CPU clock
Prescaler clock
Counter value
The counter can be cleared upon a reset, software clear (TCLR), a match with the compare
clear register, the Write Timing signal or the Position Detection signal. By a reset, the counter
is immediately cleared. By a match with the compare clear register, software clear (TCLR), the
Write Timing signal or the Position Detection signal, the counter is cleared in synchronization
with the count timing.
MCLK
Compare
register value
Prescaler clock
Compare match
Counter value
MN702-00009-1v0-E
Figure 21.5-29 16-bit Timer Count Timing
N+1
N
Figure 21.5-30 16-bit Timer Clear Timing
N - 1
N
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
N+2
N
0x0000
21.5 Operations
N+3
N+4
0x0001
0x0002
423
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