Fujitsu MB95630H Series Hardware Manual page 344

8-bit microcontroller new 8fx

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CHAPTER 18 8/16-BIT PPG

18.7 Registers

[bit3] POEN0: Output enable bit

This bit enables or disables the PPG timer n0 pin output.

In 16-bit PPG mode, since the 8/16-bit PPG outputs pulse wave through the PPG timer n0 pin, this bit

controls the 8/16-bit PPG output.

[bit2:0] CKS0[2:0]: Operating clock select bits

These bits select the operating clock for 8-bit downcounter of the PPG timer n0.

The operating clock is generated from the prescaler. For details, see "3.9 Operation of Prescaler".

In 8-bit prescaler + 8-bit PPG mode, the rising and falling edge detection pulses from the PPG timer n1

output are used as the count clock for PPG timer n0. Therefore, the settings of these bits have no effect on

In 16-bit PPG mode, use these bits to select the operating clock.

Writing "000"

Writing "001"

Writing "010"

Writing "011"

Writing "100"

Writing "101"

Writing "110"

Writing "111"

Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS0[2:0]

to "0b110" or "0b111" is prohibited.

The PPG timer n0 pin functions as a general-purpose I/O port.

The PPG timer n0 pin functions as a PPG output pin.

(MCLK: machine clock, F

: main CR clock, F

FUJITSU SEMICONDUCTOR LIMITED

: main clock,

: main CR PLL clock)

MB95630H Series

MN702-00009-1v0-E