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MB95630H Series
■ Acknowledgment
An acknowledgment is sent by the receiver in the ninth clock cycle for data byte transfer by the
sender based on the following conditions.
An address acknowledgment is generated in the following cases.
•
The received address matches the address set in IAARn, and the address acknowledgment
is output automatically (IBCR0n:AACKX = 0).
•
A general call address (0x00) is received and the general call address acknowledgment
output is enabled (IBCR1n:GACKE = 1).
A data acknowledge bit used when data is received can be enabled or disabled by the
IBCR1n:DACKE bit. In master mode, a data acknowledgment is generated if IBCR1n:DACKE
= 1. In slave mode, a data acknowledgment is generated if an address acknowledgment has
already been generated and IBCR1n:DACKE = 1. The received acknowledgment is saved in
IBSRn:LRB in the ninth SCLn cycle.
•
If the data ACK depends on the content of received data (such as packet error checking
used by the SM bus), control the data ACK by setting the data ACK enable bit
(IBCR1n:DACKE) after writing "1" to the IBCR0n:INTS bit (for example, by a previous
transfer completion interrupt) so that the latest received data can be read.
•
The latest data ACK (IBSRn:LRB) can be read after the ACK has been received
(IBSRn:LRB must be read during the transfer completion interrupt triggered by the ninth
SCLn cycle). Accordingly, if ACK is read when the IBCR0n:INTS bit is "1", you must
write "0" to this bit in the transfer completion interrupt triggered by the eighth SCLn cycle
so that another transfer completion interrupt will be triggered by the ninth SCLn cycle.
MN702-00009-1v0-E
24.6 Operations and Setting Procedure Example
FUJITSU SEMICONDUCTOR LIMITED
2
CHAPTER 24 I
C BUS INTERFACE
505
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