Fujitsu MB95630H Series Hardware Manual page 448

8-bit microcontroller new 8fx
Hide thumbs Also See for MB95630H Series:
Table of Contents

Advertisement

CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
[bit4:2] OPS[2:0]: Data transfer method select bits
These bits control the output timing of OPT5 to OPT0 pins and select the write timing control operation
mode.
Data is transferred from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) to
the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) at the write timing controlled by the
selected operation mode.
bit4:2
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
[bit1] WTIF: Write timing interrupt request flag bit
This bit is an interrupt request flag for the output timing switch set by a write signal.
When data in the OPDBRHx and OPDBRLx registers specified by the BNKF bit and RDA[2:0] bits in
OPDUR is transferred to OPDUR and OPDLR at the rising edge of the write signal, the WTIF bit is set to
"1".
With the write timing interrupt already enabled (WTIE = 1), when the WTIF bit is set to "1", a write timing
interrupt is generated.
Writing "0" to this bit clears it. Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit1
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit0] WTIE: Write timing interrupt enable bit
This bit enables or disables the write timing interrupt.
When this bit is set to "1", and the write timing interrupt request flag bit (WTIF) is also set to "1", a write
timing interrupt is generated.
bit0
Writing "0"
Writing "1"
428
Data is written to OPDBRHx/OPDBRLx by the software, and then is transferred from
OPDBRHx/OPDBRLx to OPDUR/OPDLR.
An underflow in the 16-bit reload timer triggers data transfer from OPDBRHx/OPDBRLx to
OPDUR/OPDLR.
Position detection input triggers data transfer from OPDBRHx/OPDBRLx to OPDUR/OPDLR.
The write signal generated by an underflow in the 16-bit reload timer triggers data transfer from
OPDBRHx/OPDBRLx to OPDUR/OPDLR.
The 16-bit reload timer is started by the position detection comparison circuit
The write signal generated by either an underflow in the 16-bit reload timer or position detection
input triggers data transfer from OPDBRHx/OPDBRLx to OPDUR/OPDLR.
One-shot position detection or timer underflow
One-shot position detection
One-shot position detection and timer underflow
Indicates that no write timing interrupt request has been generated.
Indicates that a write timing interrupt request has been generated.
Clears this bit.
Has no effect on operation.
Disables the write timing interrupt.
Enables the write timing interrupt.
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Details
Details
Details
MN702-00009-1v0-E

Advertisement

Table of Contents
loading

Table of Contents