16-Bit Mpg Timer Control Status Register (Tcsr) - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
21.6.8

16-bit MPG Timer Control Status Register (TCSR)

The 16-bit MPG timer control status register (TCSR) controls the operation of
the 16-bit timer.
■ Register Configuration
bit 7
Field TCLR
Attribute R/W
Initial value 0
■ Register Functions
[bit7] TCLR: Timer clear bit
The read value of this bit is always "0".
Writing "1" to this bit initializes the counter of the 16-bit timer to "0x0000".
Writing "0" to this bit has no effect on operation.
bit7
Read access
Writing "0"
Writing "1"
[bit6] MODE: Timer reset condition bit
This bit sets the reset condition for the 16-bit timer.
bit6
Writing "0"
Writing "1"
Note: The 16-bit timer is reset upon a change in the 16-bit timer value.
[bit5] ICLR: Compare clear interrupt request flag bit
This bit is the compare clear interrupt request flag.
When the value of the 16-bit MPG compare clear register (upper/lower) (CPCUR/CPCLR) match the 16-bit
timer value, the counter of the 16-bit timer is cleared and this bit is set to "1".
With the compare clear interrupt request already enabled (TCSR:ICRE = 1), when the ICLR bit is set to "1",
a compare clear interrupt is generated.
Writing "0" to this bit clears it. Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit5
Reading "0"
Reading "0"
Writing "0"
Writing "1"
MN702-00009-1v0-E
6 5
MODE ICLR
R/W R/W
0 0
The read value is always "0".
Has no effect on operation.
Initializes the counter of the 16-bit timer to "0x0000".
The 16-bit timer is reset at a write timing signal.
The 16-bit timer is reset at a position detection signal.
Indicates that no compare clear interrupt request has been generated.
Indicates that a compare clear interrupt request has been generated.
Clears this bit.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
4 3
ICRE TMEN
R/W R/W
0 0
Details
Details
Details
21.6 Registers
2 1
CLK2 CLK1
R/W R/W
0 0
0
CLK0
R/W
0
447