Fujitsu MB95630H Series Hardware Manual page 484

8-bit microcontroller new 8fx
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CHAPTER 22 UART/SIO
22.6 Operations and Setting Procedure Example
The baud rate in clock asynchronous mode (UART) can be set in the following range.
Table 22.6-3 Baud Rate Setting Range in Clock Asynchronous Mode (UART)
● Transfer data format
UART can treat data only in NRZ (Non-Return-to-Zero) format. Figure 22.6-2 shows the data
format.
The character bit length can be selected from among 5 to 8 bits depending on the settings of
SMC1n:CBL[1:0].
The stop bit length can be set to 1 or 2 bits depending on the setting of SMC1n:SBL.
The PEN bit and TDP bit in the SMC1n register can be used to enable/disable parity and to
select parity polarity.
As shown in Figure 22.6-2, the transfer data always starts from the start bit ("L" level) and ends
with the stop bit ("H" level) by performing the specified data bit length transfer with MSB first
or LSB first ("LSB first" or "MSB first" can be selected by the BDS bit in the SMC1n register).
It becomes "H" level at the idle state.
ST
D0
ST
D0
ST
D0
ST
D0
Note: 6-bit data and 7-bit data have the same data format as 5-bit data.
ST
D0
ST
D0
ST
D0
D1
ST
D0
ST
: Start bit
SP
: Stop bit
P
: Parity bit
D0 to D7: Data. The sequence can be selected from "LSB first" or "MSB first" by the
direction control register (BDS bit)
464
PSS[1:0]
0b00 to 0b11
Figure 22.6-2 Transfer Data Format
D1
D2
D4
D3
SP
D1
D2
D3
D4
SP
P
D1
D2
D3
D4
P
D1
D2
D3
D4
D1
D2
D3
D4
D5
D2
D4
D5
D1
D3
D2
D3
D4
D5
D1
D2
D3
D4
D5
FUJITSU SEMICONDUCTOR LIMITED
BRS[7:0]
0x02 (2) to 0xFF (255)
Without P
SP
SP
With P
SP
SP
D6
D7
SP
D6
D7
SP
SP
D6
D7
P
SP
D6
D7
P
SP
SP
MB95630H Series
5-bit data
Without P
8-bit data
With P
MN702-00009-1v0-E

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