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MB95630H Series
• The latest data acknowledge (IBSRn:LRB) can be read after the acknowledge has been received (IBSRn:LRB
must be read during the transfer completion interrupt in the ninth SCLn cycle.) If acknowledge is read when
this bit is "1", therefore, you must write "0" to this bit in the transfer completion interrupt in the eighth SCLn
cycle so that another transfer completion interrupt will occur in the ninth SCLn cycle.
bit6
Writing "0"
Writing "1"
[bit5] ALF: Arbitration lost interrupt request flag bit
This bit detects the arbitration lost.
An arbitration lost interrupt request is generated if this bit and the IBCR0n:ALE bit are both "1".
If one of the following conditions is satisfied, this bit is set to "1".
• An arbitration lost is detected when this device is transmitting data/address as a master.
• "1" is written to the IBCR1n:MSS bit with the I
written to the MSS bit after this device returns AACK or GACK as a slave, the ALF bit is not set to "1".
If one of the following conditions is satisfied, this bit is set to "0".
• With IBSRn:BB = 0, "0" is written to the ALF bit.
• "0" is written to the IBCR1n:INT bit to clear the transmission completion flag bit.
Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit5
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit4] ALE: Arbitration lost interrupt enable bit
This bit enables or disables the arbitration lost interrupt.
When this bit and the ALF bit are both set to "1", an arbitration lost interrupt request is generated.
bit4
Writing "0"
Writing "1"
[bit3] SPF: STOP detection interrupt request flag bit
This bit detects the STOP condition.
When this bit and the IBCR0n:SPE bit are both set to "1", a STOP detection interrupt request is generated.
With the bus busy, when a valid STOP condition is correctly detected, this bit is set to "1".
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit3
Reading "0"
Reading "1"
Writing "0"
Writing "1"
MN702-00009-1v0-E
Sets the INT bit to "1" in the ninth SCLn cycle.
Sets the INT bit to "1" in the eighth SCLn cycle.
Indicates that no arbitration lost has been detected.
Indicates that an arbitration lost has been detected.
Clears this bit.
Has no effect on operation.
Disables the arbitration lost interrupt.
Enables the arbitration lost interrupt.
Indicates that no STOP condition has been detected.
Indicates that a STOP condition has been detected.
Clears this bit.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 24 I
Details
2
C bus being used by another system. However, when "1" is
Details
Details
Details
2
C BUS INTERFACE
24.7 Registers
515
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