Fujitsu MB95630H Series Hardware Manual page 492

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Table of Contents

CHAPTER 22 UART/SIO

22.6 Operations and Setting Procedure Example

● Reception in UART/SIO operation mode 1

For reception in operation mode 1, each register is used as shown below.

Figure 22.6-11 Registers Used for Reception in Operation Mode 1

SMC1n (UART/SIO serial mode control register 1)

SMC2n (UART/SIO serial mode control register 2)

SSRn (UART/SIO serial status and data register)

TDRn (UART/SIO serial output data register)

RDRn (UART/SIO serial input data register)

× : Unused bit

1 : Set to "1"

0 : Set to "0"

The reception depends on whether the serial clock has been set to external or internal clock.

When the reception operation enable bit (RXE) contains "1", serial data is received always at

the rising edge of the external clock signal.

The serial clock signal is output in accordance with transmission. Therefore, transmission

must be performed even when only performing reception. The following two procedures can

Set the transmission operation enable bit (TXE) to "1", then write transmit data to the

UART/SIO serial output data register to generate the serial clock signal and start reception.

Write transmit data to the TDRn register, then set the TXE bit to "1" to generate the serial

clock signal and start reception.

FUJITSU SEMICONDUCTOR LIMITED

MB95630H Series

MN702-00009-1v0-E