Clock Monitoring Control Register (Cmcr) - Fujitsu MB95630H Series Hardware Manual

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Table of Contents

CHAPTER 17 CLOCK SUPERVISOR COUNTER

17.4 Registers

Clock Monitoring Control Register (CMCR)

The clock monitoring control register (CMCR) is used to select the counter

source clock, select a time-base timer interval as the counter enable period,

start the counter and check whether the counter is running or not.

■ Register Configuration

Initial value

■ Register Functions

[bit7:6] Undefined bits

Their read values are always "0". Writing values to these bits has no effect on operation.

[bit5] Reserved bit

Always set this bit to "0".

[bit4] CMCSEL: Counter clock select bit

This bit selects the counter clock source.

[bit3:1] TBTSEL[2:0]: Time-base timer counter output select bits

These bits select the time-base timer interval.

The operation of the clock supervisor counter is enabled and disabled at specific times according to the time-

base timer counter output selected by these bits.

The first rising edge of the interval selected enables the counter operation and the second rising edge of the

same output disables the counter operation.

Writing "000"

Writing "001"

Writing "010"

Writing "011"

Writing "100"

Writing "101"

Writing "110"

Writing "111"

Selects the external main oscillation clock as the source clock of the counter.

Selects the external sub-oscillation clock as the source clock of the counter.

FUJITSU SEMICONDUCTOR LIMITED

: main CR clock)

MB95630H Series

MN702-00009-1v0-E