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CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.3 Operations
Table 17.3-1 is calculated by the following equation:
If the time-base timer interrupt is used to make the clock supervisor counter wait for the
oscillation stabilization time, please satisfy the following condition:
Time-base Timer Interval > Main/Sub-oscillation Stabilization Time
e.g. F
CH
Time-base Timer Interval >
TBC[3:0] = 0b0110 (2
Notes:
• See "7.1 Overview" for time-base timer interval settings.
• See "3.3.3 Oscillation Stabilization Wait Time Setting Register (WATR)" for main/
sub-oscillation stabilization time settings.
296
3
× 1/F
2
CRH
5
× 1/F
2
CRH
7
× 1/F
2
CRH
9
× 1/F
2
CRH
11
× 1/F
2
CRH
13
× 1/F
2
CRH
15
× 1/F
2
CRH
17
× 1/F
2
CRH
Counter value =
*Omit the decimal places of "Value".
Selected time-base
timer interval
= 4 MHz, F
= 1 MHz, MWT[3:0] = 0b1111 (in WATR register)
CRH
13 ×
1/F
FUJITSU SEMICONDUCTOR LIMITED
(TBTSEL=000)
(TBTSEL=001)
(TBTSEL=010)
× Main/Sub-Oscillation Clock Frequency
(TBTSEL=011)
(TBTSEL=100)
(TBTSEL=101)
(TBTSEL=110)
(TBTSEL=111)
2
Within this period, the "Value" in the above equation is
counted by the main/sub oscillation clock.
14
(
2 )
2
–
×
≈
-----------------------
1.05
4.3ms
6
×
4
10
)
CRH
MB95630H Series
± 1 (Measurement error)
×
1.05
MN702-00009-1v0-E
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