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IDT Switch Partitions
Notes
PES48H12G2 User Manual
The partition fundamental reset condition is considered to persist as long as the STATE field in the
SWPARTxCTL register remains in the fundamental reset state. Transitioning a partition from the funda-
mental reset state to the active state requires that the system meet the requirements associated with a
conventional reset outlined in Section 6.6.1 in the PCIe Base specification.
Active
A partition in the active state is in the normal operating mode.
Partition State Change
This section describes requirements and restrictions that apply when modifying a partition's state. In
general, the state of a partition may be modified at any time, except for the restrictions listed in the sub-
sections below. Since a partition state change may take a significant amount of time to complete, status bits
are provided to indicate when the change has started and when it has completed.
– The Switch Partition State Change Initiated (SCI) bit in the Switch Partition Status
(SWPARTxSTS) register is set when a state change begins.
– The Switch Partition State Change Completed (SCC) bit in the Switch Partition Status
(SWPARTxSTS) register is set when a state change completes.
Partition state change requirements and restrictions differ based on the method used to program the
SWPARTxCTL register.
Partition State Change Latency
Partition state changes typically complete within a few clock cycles, unless the following conditions are
true. When the partition state change causes a fundamental reset in the partition (i.e., partition state set to
fundamental reset), the latency to complete the state change is 250 microseconds. This delay ensures that
the ingress and egress buffers of ports associated with the partition are fully drained before the partition
state change completes.
In addition, when the partition state change has the side-effect of modifying the operating mode of one
or more ports (e.g., partition is placed in the disabled state), the partition state change completes after the
operating mode of the ports in the partition is changed. Refer to section Port Operating Mode Change on
page 6-7 for details on the latency port operating mode changes.
Partition State Change via EEPROM Loading
When modifying the state of a partition via the serial EEPROM, it is not possible to check the SCI and
SCC bits in the SWPARTxSTS register to obtain an indication of partition state change initiation and
completion. As a result, the following requirements and restrictions apply:
– The state of a partition can only be modified when there are no ports associated with the partition
(i.e., the partition is empty). Violating this rule produces undefined results.
– Prior to modifying the state of a partition, it is required that the following proprietary timer registers
be set to 0x0. This will ensure instantaneous execution of the partition state change action. The
last instructions in the EEPROM must set these timers back to their default values.
• Side Effect Delay Timer (SEDELAY register)
• Port Operating Mode Change Drain Delay Timer (POMCDELAY register)
• Reset Drain Delay Timer (RDRAINDELAY register)
• Upstream Secondary Bus Reset Delay (USSBRDELAY register)
– The GPIO alternate function associated with a partition reset signal (PARTxPERSTN) must not be
1
enabled
until all partition and port configurations are performed.
– In the serial EEPROM, the instructions that execute partition and port configurations must be
placed before the instruction that enables a GPIO alternate function associated with a partition
reset signal (PARTxPERSTN). The instruction that enables the PARTxPERSTN GPIO alternate
function may immediately follow the last instruction that configured a partition state and/or port
mode.
1.
Refer to Chapter 12 for details on enabling alternate functionality on GPIO signals.
6 - 3
April 5, 2013
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