Renesas IDT 89HPES48H12AG2 Manuals

Manuals and User Guides for Renesas IDT 89HPES48H12AG2. We have 1 Renesas IDT 89HPES48H12AG2 manual available for free PDF download: User Manual

Renesas IDT 89HPES48H12AG2 User Manual (327 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 4 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
4
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
7
Reference Documents
7
Table of Contents
11
PES48H12AG2 Device Overview
25
Introduction
25
Features
25
Logic Diagram
29
System Identification
30
Vendor ID
30
Device ID
30
Revision ID
30
Jtag ID
30
Ssid/Ssvid
30
Device Serial Number Enhanced Capability
30
PES48H12AG2 Device Ids
30
Table 1.3 PES48H12AG2 Revision ID
30
Pin Description
31
Table 1.4 PCI Express Interface Pins
31
Table 1.5 Reference Clock Pins
32
Table 1.6 Smbus Interface Pins
32
Table 1.7 General Purpose I/O Pins
33
Table 1.8 System Pins
39
Table 1.9 Test Pins
41
Table 1.10 Power, Ground, and Serdes Resistor Pins
41
Pin Characteristics
43
Table 1.11 Pin Characteristics
43
Architectural Overview
47
Introduction
47
Switch Partitioning
48
Dynamic Reconfiguration
49
Switch Core
51
Introduction
51
Switch Core Architecture
51
Ingress Buffer
51
Table 3.1 IFB Buffer Sizes
51
Egress Buffer
52
Table 3.2 EFB Buffer Sizes
52
Crossbar Interconnect
53
Datapaths
53
Table 3.3 Replay Buffer Storage Limit
53
Packet Ordering
54
Arbitration
55
Table 3.4 Packet Ordering Rules in the PES48H12AG2
55
Port Arbitration
56
Cut-Through Routing
56
Table 3.5 Conditions for Cut-Through Transfers
57
Request Metering
58
Operation
60
Table 1.1 Table
60
Table 3.6 Request Metering Decrement Value
61
Completion Size Estimation
62
Internal Errors
63
Switch Time-Outs
64
Memory SECDED ECC Protection
64
End-To-End Data Path Parity Protection
64
Clocking
67
Port Clocking Modes
68
Spread Spectrum Clocking (SSC) Support
68
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State
68
Table 4.2 GCLK and Pxclk Frequencies When Pxclk Has SSC
69
Table 4.3 Port Clocking Mode Requirements
69
Table 4.4 Valid PES48H12AG2 System Clocking Configurations
69
Global Clocked Mode
70
Local Port Clocked Mode
71
Modification of a Port's Clock Mode
72
Table 4.5 Clock Frequency Limitations When Modifying a Port's Clock Mode
72
Reset and Initialization
73
Introduction
73
Table 5.1 PES48H12AG2 Reset Precedence
73
Boot Configuration Vector
74
Table 5.2 Boot Configuration Vector Signals
74
Switch Fundamental Reset
75
Switch Mode Dependent Initialization
78
Table 5.3 Switch Mode Dependent Register Initialization
78
Port Merging
79
Partition Resets
80
Partition Fundamental Reset
80
Partition Hot Reset
81
Partition Upstream Secondary Bus Reset
81
Partition Downstream Secondary Bus Reset
82
Port Mode Change Reset
82
Switch Partitions
83
Introduction
83
Partition Configuration
83
Partition State
84
Partition State Change
85
Switch Ports
86
Switch Port Mode
86
Port Operating Mode Change
89
Common Operating Mode Change Behavior
91
No Action Mode Change Behavior
96
Reset Mode Change Behavior
96
Hot Reset Mode Change Behavior
97
Partition and Port Configuration
97
Static Reconfiguration
97
Dynamic Reconfiguration
98
Link Operation
101
Introduction
101
Polarity Inversion
101
Lane Reversal
101
Link Width Negotiation
105
Link Width Negotiation in the Presence of Bad Lanes
106
Dynamic Link Width Reconfiguration
106
Link Speed Negotiation
106
Link Speed Negotiation in the PES48H12AG2
107
Software Management of Link Speed
108
Link Retraining
109
Link down
110
Slot Power Limit Support
110
Upstream Port
110
Downstream Port
110
Link States
111
Active State Power Management
111
L0S ASPM
112
L1 Aspm
112
L1 ASPM Entry Rejection Timer
113
Link Status
114
De-Emphasis Negotiation
114
Crosslink
115
Table 7.1 Crosslink Port Groups
115
Hot Reset Operation on a Crosslink
116
Link Disable Operation on a Crosslink
116
Gen1 Compatibility Mode
116
Table 7.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
117
Serdes
119
Introduction
119
Serdes Numbering and Port Association
119
Serdes Transmitter Controls
119
Driver Voltage Level and Amplitude Boost
119
De-Emphasis
120
Slew Rate
120
PCI Express Low-Swing Mode
120
Receiver Equalization
121
Programming of Serdes Controls
121
Programmable Voltage Margining and De-Emphasis
121
Serdes Transmitter Control Registers
122
Table 8.1 Serdes Transmit Level Controls in the S[X]Txlctl0 and S[X]Txlctl1 Registers
123
Table 8.2 Serdes Transmit Driver Settings in Gen1 Mode
124
Table 8.3 Serdes Transmit Driver Settings in Gen2 Mode with -3.5Db De-Emphasis
125
Table 8.4 Serdes Transmit Driver Settings in Gen2 Mode with -6.0Db De-Emphasis
126
Table 8.5 Transmitter Slew Rate Settings
129
Transmit Margining Using the PCI Express Link Control 2 Register
130
Table 8.6 PCI Express Transmit Margining Levels Supported by the PES48H12AG2
130
Low-Swing Transmitter Voltage Mode
131
Table 8.7 Serdes Transmit Drive Swing in Low Swing Mode at Gen1 Speed
131
Receiver Equalization Controls
132
Table 8.8 Serdes Transmit Drive Swing in Low Swing Mode at Gen2 Speed
132
Serdes Power Management
133
Theory of Operation
135
Introduction
135
Transaction Routing
135
Interrupts
135
Table 9.1 Switch Routing Methods
135
Downstream Port Interrupts
136
Legacy Interrupt Emulation
136
Table 9.2 Downstream Port Interrupts
136
Access Control Services
137
Table 9.3 Downstream to Upstream Port Interrupt Routing Based on Device Number
137
Table 9.4 Prioritization of ACS Checks for Request Tlps
139
Error Detection and Handling
140
Table 9.5 Prioritization of ACS Checks for Completion Tlps
140
Table 9.6 TLP Types Affected by ACS Checks
140
Physical Layer Errors
141
Data Link Layer Errors
141
Table 9.7 Physical Layer Errors
141
Table 9.8 Data Link Layer Errors
141
Transaction Layer Errors
142
Table 9.9 Transaction Layer Errors Associated with the PCI-To-PCI Bridge Function
143
Table 9.10 Conditions Handled as Unsupported Requests (UR) by the PCI-To-PCI Bridge Function
145
Table 9.11 Ingress TLP Formation Checks Associated with the PCI-To-PCI Bridge Function
145
Table 9.12 Egress Malformed TLP Error Checks
146
Table 9.13 ACS Violations for Ports Operating in Downstream Switch Port Mode
147
Table 9.14 Prioritization of Transaction Layer Errors
148
Table 10.1 Table
149
Routing Errors
150
Bus Locking
151
Hot-Plug and Hot-Swap
155
Introduction
155
Hot-Plug Signals
157
Port Reset Outputs
159
Power Enable Controlled Reset Output
159
Hot-Plug Events
160
Power Good Controlled Reset Output
160
Legacy System Hot-Plug Support
161
Hot-Swap
162
Power Management
163
Introduction
163
Table 11.1 PES48H12AG2 Power Management State Transition Diagram
164
PME Messages
165
PCI Express Power Management Fence Protocol
165
Upstream Switch Port or Downstream Switch Port Mode
165
Power Budgeting Capability
166
General Purpose I/O
167
Introduction
167
GPIO Configuration
167
Configured as an Input
167
Configured as an Output
167
Configured as an Alternate Function
167
Table 12.1 GPIO Pin Configuration
167
Table 12.2 General Purpose I/O Pin Alternate Function
168
Table 12.3 GPIO Alternate Function Pins
169
Smbus Interfaces
171
Introduction
171
Master Smbus Interface
171
Initialization
171
Figure 13.1 Split Smbus Interface Configuration
171
Serial EEPROM
172
Initialization from Serial EEPROM
172
Table 13.1 Serial EEPROM Smbus Address
172
Table 13.2 PES48H12AG2 Compatible Serial Eeproms
172
Figure 13.2 Single Double Word Initialization Sequence Format
173
Figure 13.3 Sequential Double Word Initialization Sequence Format
174
Figure 13.4 Configuration Done Sequence Format
174
Programming the Serial EEPROM
175
Table 13.3 Serial EEPROM Initialization Errors
175
I/O Expanders
176
Table 13.4 I/O Expander Function Allocation
176
Table 13.5 I/O Expander Default Output Signal Value
177
Table 13.7 Pin Mapping I/O Expander 8
180
Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs
182
Table 13.11 I/O Expander 12 - Link up Status
183
Slave Smbus Interface
184
Initialization
184
Table 13.12 I/O Expander 13 - Link Activity Status
184
Table 13.13 Slave Smbus Address
184
Smbus Transactions
185
Table 13.14 Slave Smbus Command Code Fields
185
Figure 13.5 Slave Smbus Command Code Format
185
Table 13.15 CSR Register Read or Write Operation Byte Sequence
186
Figure 13.6 CSR Register Read or Write CMD Field Format
186
Table 13.16 CSR Register Read or Write CMD Field Description
187
Table 13.17 Serial EEPROM Read or Write Operation Byte Sequence
187
Table 13.18 Serial EEPROM Read or Write CMD Field Description
188
Figure 13.7 Serial EEPROM Read or Write CMD Field Format
188
Figure 13.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
189
Figure 13.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
189
Figure 13.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
189
Figure 13.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
190
Figure 13.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
190
Figure 13.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
190
Multicast
191
Introduction
191
Addressing and Routing
191
Multicast TLP Determination
191
Figure 14.1 Multicast Group Address Ranges
192
Figure 14.2 Multicast Group Address Region Determination
193
Multicast TLP Routing
194
Multicast Egress Processing
194
Register Organization
197
Introduction
197
Table 15.1 Global Address Space Organization
197
Partial-Byte Access to Word and Dword Registers
198
Register Side-Effects
198
Address Maps
198
PCI-To-PCI Bridge Registers
199
Capability Structures
199
Table 15.2 Default PCI Capability List Linkage
200
Table 15.3 Default PCI Express Capability List Linkage
200
Figure 15.1 PCI-To-PCI Bridge Configuration Space Organization
201
Table 15.4 PCI-To-PCI Bridge Configuration Space Registers
202
IDT Proprietary Port Specific Registers
206
Figure 15.2 Proprietary Port Specific Register Organization
206
Table 15.5 Proprietary Port Specific Registers
207
Switch Configuration and Status Registers
208
Figure 15.3 Switch Configuration and Status Space Organization
208
Table 15.6 Switch Configuration and Status
209
PCI to PCI Bridge and Proprietary Port Specific Registers
215
Type 1 Configuration Header Registers
215
PCI Express Capability Structure
225
Power Management Capability Structure
241
Message Signaled Interrupt Capability Structure
243
Subsystem ID and Subsystem Vendor ID
245
Extended Configuration Space Access Registers
245
Advanced Error Reporting (AER) Enhanced Capability
246
Device Serial Number Enhanced Capability
255
PCI Express Virtual Channel Capability
256
Power Budgeting Enhanced Capability
261
ACS Extended Capability
263
Multicast Extended Capability
266
Proprietary Port Specific Registers
271
Port Control and Status Registers
271
Internal Error Control and Status Registers
273
Physical Layer Control and Status Registers
281
Power Management Control and Status Registers
284
Request Metering
284
Global Address Space Access Registers
286
Switch Configuration and Status Registers
289
Switch Control and Status Registers
289
Internal Switch Timer
292
Switch Partition and Port Registers
293
Protection
296
Serdes Control and Status Registers
296
General Purpose I/O Registers
304
Hot-Plug and Smbus Interface Registers
309
JTAG Boundary Scan
317
Introduction
317
Test Access Point
317
Signal Definitions
317
Figure 18.1 Diagram of the JTAG Logic
317
Table 18.1 JTAG Pin Descriptions
318
Figure 18.2 State Diagram of the TAP Controller
318
Boundary Scan Chain
319
Table 18.2 Boundary Scan Chain
319
Test Data Register (DR)
321
Boundary Scan Registers
321
Figure 18.3 Diagram of Observe-Only Input Cell
322
Figure 18.4 Diagram of Output Cell
322
Instruction Register (IR)
323
Figure 18.5 Diagram of Bidirectional Cell
323
Extest
324
Sample/Preload
324
Bypass
324
Table 18.3 Instructions Supported by the JTAG Boundary Scan
324
Clamp
325
Idcode
325
Validate
325
Extest_Train
325
Table 18.4 System Controller Device Identification Register
325
Figure 18.6 Device ID Register Format
325
Extest_Pulse
326
Reserved
326
Usage Considerations
326

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Renesas IDT 89HPES48H12AG2 User Manual (327 pages)

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