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Notes
PES48H12G2 User Manual
®
Introduction
All software visible registers in the PES48H12G2 are contained in a 256 KB global address space. The
address of a register in this address range is referred to as the system address of the register.
– The system address is 18-bits in size.
System addresses are used for serial EEPROM initialization and slave SMBus register access.
– The global address range is partitioned into regions as shown in Table 15.1.
– There is a 4 KB region for PCI-to-PCI bridge registers associated with each port.
– There is one 8 KB region for switch configuration and status registers.
Base Address
0x00000
0x02000
0x04000
0x06000
0x08000
0x0A000
0x0C000
0x0E000
0x10000
0x12000
0x18000
0x1A000
0x1C000 - 0x3DFFF
0x3E000 - 0x3FFFF
Other
Table 15.1 Global Address Space Organization
PCI-to-PCI bridge registers correspond to the configuration registers associated with an upstream or
downstream switch port.
– These registers are accessible as function 0 to PCI configuration requests when the port is config-
ured to operate in upstream switch port or downstream switch port.
– The PCI configuration or extended configuration space address of a PCI-to-PCI bridge register is
equal to the offset address of the register within the global address region. The offset address map
for PCI-to-PCI bridge registers is defined in section PCI-to-PCI Bridge Registers on page 15-3.
The switch configuration and status register region contains registers that control general operation of
the switch or that are proprietary in nature.
– The offset address switch configuration and status registers is defined in section Switch Configu-
ration and Status Registers on page 15-12.
Register Organization
Address Range
Port 0 PCI-to-PCI Bridge Registers
Port 1 PCI-to-PCI Bridge Registers
Port 2 PCI-to-PCI Bridge Registers
Port 3 PCI-to-PCI Bridge Registers
Port 4 PCI-to-PCI Bridge Registers
Port 5 PCI-to-PCI Bridge Registers
Port 6 PCI-to-PCI Bridge Registers
Port 7 PCI-to-PCI Bridge Registers
Port 8 PCI-to-PCI Bridge Registers
Port 9 PCI-to-PCI Bridge Registers
Port 12 PCI-to-PCI Bridge Registers
Port 13 PCI-to-PCI Bridge Registers
Reserved
Switch Configuration and Status Registers
Reserved
15 - 1
Chapter 15
April 5, 2013
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