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Notes
PES48H12G2 User Manual
®
Introduction
This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with
each PES48H12G2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI
Express lanes (i.e., a SerDes "quad"), plus a central block that controls the quad as a whole. This central
block is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each
lane, initialization of the quad, etc.
In order to improve signal integrity across the high-speed PCI Express links, the PES48H12G2 allows
per-lane programmability of several SerDes settings. These include the following.
– Transmitter drive level
– Transmitter de-emphasis level
– Transmitter slew rate
– Receiver equalization
In addition, the PES48H12G2 supports the optional "low-swing mode" specified by the PCI Express 2.0
specification. This mode is intended for power-sensitive applications.
This chapter describes these controls, their intended use, and the manner in which they are
programmed. Before this is discussed, the topic of SerDes numbering and port association is introduced. To
modify the SerDes driver and receiver settings for a port, the SerDes quad and specific lanes associated
with the port must be identified as described in the next section.
SerDes Numbering and Port Association
The PES48H12G2 contains twelve SerDes quads, numbered zero to 11. A SerDes quad is normally
associated with its corresponding numbered port (i.e., SerDes quad 0 is associated with port 0, SerDes
quad 1 is associated with Port 1, and so on).
A x4 port is always associated with its corresponding SerDes quad.
A x8 (merged) port is composed of an even numbered port and its odd counterpart. This port is always
associated with the two corresponding SerDes quads (i.e., a merged port 0 is associated with SerDes 0 and
SerDes 1, merged port 2 is associated with SerDes 2 and SerDes 3, etc.).
SerDes Transmitter Controls
The PES48H12G2 allows programmability of SerDes transmitter voltage level, de-emphasis, and slew
(i.e., signal rise and fall times), including support for the PCI Express optional low-swing mode, as well as a
proprietary "amplitude boost" feature to increase the drive strength above its normal operating level (e.g.,
for operation across long traces).
Except for low-swing mode, which is defined by PCI Express as a per-link function, all the other controls
are proprietary and provided on a per-lane basis. This allows a system designer to customize the SerDes
transmitter settings for each lane independently. At the 5.0 GT/s speed (i.e., Gen2) and above, small differ-
ences in the channel characteristics among lanes may result in noticeable differences in the quality of the
signal at the receiver and per-lane controllability is an important tool in improving the bit-error rate on the
link.
Driver Voltage Level and Amplitude Boost
The PCI Express 2.0 specification requires that each port support the 'transmit margining' feature. This
feature allows the selection of several voltage settings across the link and is intended for compliance testing
and debug.
8 - 1
Chapter 8
SerDes
April 5, 2013
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