Renesas IDT 89HPES12NT12G2 Manuals

Manuals and User Guides for Renesas IDT 89HPES12NT12G2. We have 2 Renesas IDT 89HPES12NT12G2 manuals available for free PDF download: User Manual, Hardware Design Manual

Renesas IDT 89HPES12NT12G2 User Manual (723 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 8 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
4
Numeric Representations
5
Data Units
5
Register Terminology
6
Use of Hypertext
7
Reference Documents
7
Revision History
7
Table of Contents
11
PES12NT12G2 Device Overview
37
Overview
37
System Identification
37
Vendor ID
37
Device ID
37
Revision ID
37
PES12NT12G2 Device Ids
37
Jtag ID
38
Ssid/Ssvid
38
Device Serial Number Enhanced Capability
38
Architectural Overview
38
Port Operating Modes
39
Switch Partitioning
42
Table 1.3 Operating Modes Supported by each Port
42
Figure 1.3 Transparent PCI Express Switch
42
Figure 1.4 Partitionable PCI Express Switch
43
Non-Transparent Operation
44
Figure 1.5 Non-Transparent Bridge
44
Figure 1.6 Generalized Multi-Port Non-Transparent Interconnect
45
Figure 1.7 Architectural Approaches for Integrating Non-Transparency into a PCI Express Switch
46
Figure 1.8 Non-Transparent Switch with Non-Transparency between Partitions
47
Figure 1.9 Non-Transparent Switch with Non-Transparent Ports
47
DMA Operation
48
Figure 1.10 Switch Partition with DMA Function
49
Dynamic Reconfiguration and Failover
50
Figure 1.11 Two Switch Partitions Interconnected by an NTB, with DMA in One Partition
50
Figure 1.12 Two Switch Partitions Interconnected by an NTB, with DMA in both Partitions
50
Figure 1.13 Non-Transparent Switch Failover Usage
51
Switch Events
52
Figure 1.14 Example of Switch Event Mechanism
52
Multicasting and Non-Transparent Multicasting
53
Figure 1.15 Example of Transparent Multicast
53
Figure 1.16 Example of Non Transparent Multicast
54
Clocking
55
Overview
55
Port Clocking Modes
56
Table 2.1 Ports that Must Operate with the same Port Clocking Mode
56
Figure 2.1 Logical Representation of PES12NT12G2 Clocking Architecture
56
Global Clocked Mode
57
Figure 2.2 Clocking Connection for a Port in Global Clocked Mode, with a Common Clocked
57
Figure 2.3 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked
57
Local Port Clocked Mode
58
Table 2.2 Pxclk Usage When a Port Operates in Local Port Clocked Mode
58
Figure 2.4 Clocking Connection for a Port in Local Port Clocked Mode, in a Common Clocked
58
Support for Spread Spectrum Clocking (SSC)
59
Figure 2.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common
59
Port Clocking Mode Selection
60
Table 2.3 GCLK and Pxclk Frequencies When Pxclk Has SSC
60
Table 2.4 Port Clocking Mode Requirements
60
Table 2.5 Initial Port Clocking Mode and Slot Clock Configuration State
61
Table 2.6 Clock Frequency Limitations When Modifying a Port's Clock Mode
61
System Clocking Configurations
62
Table 2.7 Valid PES12NT12G2 System Clocking Configurations
62
Reset and Initialization
63
Overview
63
Table 3.1 PES12NT12G2 Reset Precedence
63
Switch Fundamental Reset
64
Figure 3.1 Switch Fundamental Reset with Serial EEPROM Initialization
65
Boot Configuration Vector
66
Figure 3.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
66
Stack Configuration
67
Table 3.2 Boot Configuration Vector Signals
67
Table 3.3 Ports in each Stack
68
Table 3.4 Configuration for Stack 0
68
Table 3.5 Possible Configurations for Stack 2
68
Static Configuration of a Stack
69
Table 3.6 Possible Configurations for Stack 3
69
Dynamic Reconfiguration of a Stack Via EEPROM / Smbus
70
Switch Modes
70
Table 3.7 Normal Switch Modes
70
Table 3.8 Switch Mode Dependent Register Initialization
71
Partition Resets
72
Partition Fundamental Reset
72
Partition Hot Reset
73
Partition Upstream Secondary Bus Reset
74
Partition Downstream Secondary Bus Reset
74
Port Mode Change Reset
75
Switch Core
77
Overview
77
Switch Core Architecture
77
Ingress Buffer
78
Figure 4.1 High Level Diagram of Switch Core
78
Egress Buffer
79
Table 4.1 IFB Buffer Sizes
79
Crossbar Interconnect
80
Table 4.2 EFB Buffer Sizes
80
Table 4.3 Replay Buffer Storage Limit
80
Virtual Channel Support
81
Packet Routing Classes
81
Packet Ordering
82
Arbitration
82
Port Arbitration
82
Table 4.4 Packet Ordering Rules in the PES12NT12G2
82
Figure 4.2 Architectural Model of Arbitration
83
Cut-Through Routing
85
Table 4.5 Conditions for Cut-Through Transfers
86
Request Metering
87
Figure 4.3 PCI Express Switch Static Rate Mismatch
88
Operation
89
Figure 4.4 PCI Express Switch Static Rate Mismatch
89
Completion Size Estimation
90
Table 4.6 Request Metering Decrement Value
90
Figure 4.5 Request Metering Counter Decrement Operation
90
Figure 4.6 Non-Posted Read Request Completion Size Estimate Computation
91
Internal Errors
92
Switch Core Time-Outs
93
Figure 4.7 Internal Error Logic in each PES12NT12G2 Port
93
Memory SECDED ECC Protection
94
End-To-End Data Path Parity Protection
94
Reporting of Port AER Errors as Internal Errors
95
Figure 4.8 Reporting of Port AER Errors as Internal Errors
97
Switch Partition and Port Configuration
99
Overview
99
Switch Partitions
99
Partition Configuration
100
Partition State
101
Partition State Change
102
Figure 5.1 Allowable Partition State Transitions
102
Switch Ports
103
Switch Port Mode
103
Figure 5.2 Logical Representation of a Port with PCI-To-PCI Bridge, NT, and DMA Functions
104
Table 5.1 Port Functions for each Port Operating Mode
105
Port Operating Mode Change
111
Table 5.2 Port Operating Mode Changes Supported by the Switch
112
Common Operating Mode Change Behavior
113
No Action Mode Change Behavior
119
Reset Mode Change Behavior
120
Partition Reconfiguration and Failover
120
Partition Reconfiguration Latency
121
System Notification of Partition Reconfiguration
121
Failover
123
Overview
123
Failover Initiation
123
Figure 6.1 Failover Policy Vs. Failover Reconfiguration
123
Software Initiated Failover
124
Signal Initiated Failover
124
Watchdog Timer Initiated Failover
124
Link Operation
127
Overview
127
Port Merging
127
Port Maximum Link Width
127
Polarity Inversion
128
Lane Reversal
128
Figure 7.1 Lane Reversal for Highest Achievable Link Width of X2
128
Figure 7.2 Lane Reversal for Highest Achievable Link Width of X4
129
Link Width Negotiation
130
Figure 7.3 Lane Reversal for Highest Achievable Link Width of X8
130
Link Width Negotiation in the Presence of Bad Lanes
131
Dynamic Link Width Reconfiguration
131
Dynamic Link Width Reconfiguration in the PES12NT12G2
132
Link Speed Negotiation
132
Link Speed Negotiation in the PES12NT12G2
133
Software Management of Link Speed
134
Link Retraining
135
Link States
135
Link down Handling
136
Figure 7.4 PES12NT12G2 ASPM Link State Transitions
136
Slot Power Limit Support
137
Upstream Port
137
Downstream Switch Port
138
Link Active State Power Management (ASPM)
138
L0S ASPM
138
L1 Aspm
139
Link Status
142
De-Emphasis Negotiation
142
Crosslink
143
Hot Reset Operation on a Crosslink
143
Link Disable Operation on a Crosslink
143
Table 7.1 Crosslink Port Groups
143
Gen 1 Compatibility Mode
144
Table 7.2 Gen 1 Compatibility Mode: Bits Cleared in Training Sets
144
Serdes
145
Overview
145
Serdes Numbering and Port Association
145
Serdes Transmitter Controls
146
Driver Voltage Level and Amplitude Boost
147
De-Emphasis
147
PCI Express Low-Swing Mode
147
Receiver Equalization
147
Programming of Serdes Controls
148
Programmable Voltage Margining and De-Emphasis
148
Serdes Transmitter Control Registers
149
Table 8.4 Serdes Transmit Level Controls in the S[X]Txlctl0 and S[X]Txlctl1 Registers
150
Table 8.5 Serdes Transmit Driver Settings in Gen 1 Mode with -3.5 Db De-Emphasis
150
Table 8.6 Serdes Transmit Driver Settings in Gen 2 Mode with -3.5 Db De-Emphasis
151
Table 8.7 Serdes Transmit Driver Settings in Gen 2 Mode with -6.0 Db De-Emphasis
153
Figure 8.1 Relationship between Coarse and Fine De-Emphasis Controls
154
Transmit Margining Using the PCI Express Link Control 2 Register
155
Figure 8.2 Effect of Fine De-Emphasis Control at Gen 2 with -6.0 Db Nominal De-Emphasis
155
Low-Swing Transmitter Voltage Mode
156
Table 8.8 PCI Express Transmit Margining Levels Supported by the PES12NT12G2
156
Table 8.9 Serdes Transmit Drive Swing in Low Swing Mode at Gen 1 Speed
157
Table 8.10 Serdes Transmit Drive Swing in Low Swing Mode at Gen 2 Speed
157
Receiver Equalization Controls
158
Serdes Power Management
158
Power Management
161
Overview
161
Table 9.1 PES12NT12G2 Power Management State Transition Diagram
162
Figure 9.1 PES12NT12G2 Power Management State Transition Diagram
162
Power Management Event (PME) Messages
164
PCI Express Power Management Fence Protocol
164
Upstream Switch Port or Downstream Switch Port Mode
164
NT Function Mode or NT with DMA Function Mode
165
Upstream Switch Port with NT And/Or DMA Function Mode
165
Notes
167
Transparent Switch Operation
167
Overview
167
Transaction Routing
167
Table 10.1 Switch Routing Methods
167
Virtual Channel Support
168
Maximum Payload Size
168
Upstream Port Device Number
168
Bus Locking
168
Interrupts
170
Downstream Port Interrupts
170
Upstream Port Interrupts
170
Table 10.2 PCI-To-PCI Bridge Function Interrupts
170
Legacy Interrupt Aggregation
171
Figure 10.1 Logical Representation of Intx Aggregation
171
Access Control Services
172
Table 10.3 Downstream to Upstream Port Interrupt Routing Based on Device Number
172
Figure 10.2 ACS Source Validation Example
173
Figure 10.3 ACS Peer-To-Peer Request Re-Direct at a Downstream Switch Port
174
Figure 10.4 ACS Upstream Forwarding Example
174
Table 10.4 Prioritization of ACS Checks for Request Tlps
175
ECRC Support
176
Table 10.5 Prioritization of ACS Checks for Completion Tlps
176
Table 10.6 TLP Types Affected by ACS Checks
176
Error Detection and Handling by the PCI-To-PCI Bridge Function
177
Physical Layer Errors
177
Data Link Layer Errors
178
Table 10.7 Physical Layer Errors
178
Table 10.8 Data Link Layer Errors
178
Transaction Layer Errors
179
Table 10.9 Transaction Layer Errors Associated with the PCI-To-PCI Bridge Function
180
Table 10.11 Conditions Handled as Unexpected Completions (UC) by the PCI-To-PCI Bridge
182
Table 10.12 Ingress TLP Formation Checks Associated with the PCI-To-PCI Bridge Function
183
Table 10.13 Egress Malformed TLP Error Checks
184
Table 10.14 ACS Violations for Ports Operating in Downstream Switch Port Mode
185
Table 10.15 Prioritization of Transaction Layer Errors
186
Table 1.1 Table
187
Routing Errors
189
Error Emulation Control in the PCI-To-PCI Bridge Function
190
Hot-Plug and Hot-Swap
193
Overview
193
Figure 11.1 Hot-Plug on Switch Downstream Slots Application
193
Figure 11.2 Hot-Plug with Switch on Add-In Card Application
194
Figure 11.3 Hot-Plug with Carrier Card Application
194
Hot-Plug Signals
195
Table 11.1 Port Hot Plug Signals
195
Table 11.2 Negated Value of Unused Hot-Plug Output Signals
196
Port Reset Outputs
197
Power Enable Controlled Reset Output
197
Power Good Controlled Reset Output
198
Figure 11.4 Power Enable Controlled Reset Output Mode Operation
198
Figure 11.5 Power Good Controlled Reset Output Mode Operation
198
Hot-Plug Events
199
Legacy System Hot-Plug Support
199
Hot-Swap
200
Smbus Interfaces
201
Overview
201
Master Smbus Interface
201
Initialization and I 2 C Reset
201
Figure 12.1 Split Smbus Interface Configuration
201
Serial EEPROM
202
Table 12.1 Serial EEPROM Smbus Address
202
Initialization from Serial EEPROM
203
Table 12.2 PES12NT12G2 Compatible Serial Eeproms
203
Figure 12.2 Single Double-Word Initialization Sequence Format
204
Figure 12.3 Sequential Double-Word Initialization Sequence Format
205
Figure 12.4 Jump Configuration Block
205
Figure 12.5 Execution of a Jump Configuration Block
206
Figure 12.6 Example of Multiple Configuration Images in Serial EEPROM
207
Figure 12.7 Wait Configuration Block
208
Figure 12.8 Configuration Done Sequence Format
209
Programming the Serial EEPROM
210
Table 12.3 Serial EEPROM Initialization Errors
210
I/O Expanders
211
Table 12.4 I/O Expander Functionality Allocation
211
Table 12.6 I/O Expander 0 through 11 Port Mapping
216
Table 12.11 Pin Mapping I/O Expander 16
218
Table 12.14 Pin Mapping of I/O Expander 19
220
Slave Smbus Interface
222
Initialization
222
Smbus Transactions
223
Table 12.17 Slave Smbus Address
223
Table 12.18 Slave Smbus Command Code Fields
223
Figure 12.9 Slave Smbus Command Code Format
223
Table 12.19 CSR Register Read or Write Operation Byte Sequence
224
Table 12.20 CSR Register Read or Write CMD Field Description
225
Figure 12.10 CSR Register Read or Write CMD Field Format
225
Table 12.21 Serial EEPROM Read or Write Operation Byte Sequence
226
Figure 12.11 Serial EEPROM Read or Write CMD Field Format
226
Table 12.22 Serial EEPROM Read or Write CMD Field Description
227
Figure 12.12 CSR Register Read Using Smbus Block Write/Read Transactions with PEC
227
Figure 12.13 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
228
Figure 12.14 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
228
Figure 12.15 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
228
Figure 12.16 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
228
Setting up I2C Commands for Block Transactions
229
CSR Register Read or Write Operation
229
Figure 12.17 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
229
Smbus Transactions
230
Table 12.23 CSR Register Read or Write Operation Byte Sequence
230
Table 12.24 Slave Smbus Command Code Fields
231
Table 12.25 CSR Register Read or Write CMD Field Description
231
Examples of Setting up the I2C CSR Byte Sequence for a CSR Register Read
232
Table 12.26 Constants Used in Examples
232
Table 12.27 I2C Command Byte Array Indices
233
Table 12.28 I2C Command Byte Array Indices
234
Examples of Setting up the I2C CSR Byte Sequence for a CSR Register Write
235
Table 12.29 I2C Command Byte Array Indices
235
Table 12.30 I2C Command Byte Array Indices
236
Table 12.31 I2C Command Byte Array Indices
237
Table 12.32 I2C Command Byte Array Indice
238
General Purpose I/O
241
Overview
241
GPIO Configuration
241
Input
241
Output
241
Alternate Function
241
Table 13.1 GPIO Pin Configuration
241
Table 13.2 GPIO Alternate Function Pin Assignment
242
Table 13.3 GPIO Alternate Function Pins
242
Notes
243
Non-Transparent Switch Operation
243
Overview
243
Base Address Registers (Bars)
243
BAR Limit
244
Table 14.1 NT Endpoint Bars
244
Figure 14.1 BAR Limit Operation
245
Mapping NT Configuration Space to BAR 0
246
TLP Translation
246
Direct Address Translation
246
Figure 14.2 Direct Address Translation
246
Lookup Table Address Translation
247
Figure 14.3 Lookup Table Translation
247
Figure 14.4 Lookup Table Entry Format
248
Table 14.2 12-Entry Lookup Table Parameters
249
Table 14.3 24-Entry Lookup Table Parameters
250
ID Translation
251
NT Mapping Table
251
Table 14.4 NT Mapping Table Field Description
251
Figure 14.5 NT Mapping Table
251
Request ID Translation
253
Figure 14.6 NT Table Partitioning
253
Figure 14.7 Request TLP Requester ID Translation
254
Completion ID Translation
255
Figure 14.8 Request TLP Requester ID Translation
255
Requester ID Capture Register
256
TLP Attribute Processing
256
No Snoop Processing
256
Address Type Processing
257
NT Multicast
257
Inter-Domain Communications
257
Doorbell Registers
258
Message Registers
259
Figure 14.9 Logical Representation of Doorbell Operation
259
Punch-Through Configuration Requests
260
Figure 14.10 Logical Representation of Message Register Operation
260
Re-Programming the Bus Number of the NT Function
261
Interrupts
262
Figure 14.11 Example of a Rootless PCI Express Hierarchy with Bus Number Reprogramming
262
Virtual Channel Support
263
Table 14.1 NT Endpoint Interrupts
263
Maximum Payload Size
264
Power Management
264
Bus Locking
264
ECRC Support
264
Access Control Services (ACS)
265
Table 14.2 ACS Checks Performed by the NT Function in a Port Operating in Multi-Function Mode
266
Table 14.3 TLP Types Affected by ACS Checks
266
Error Detection and Handling by the NT Function
267
Figure 14.12 Example of ACS Peer-To-Peer Request Re-Direct Applied by the NT Function
267
Physical Layer Errors
268
Data Link Layer Errors
268
Transaction Layer Errors
268
Table 14.4 Transaction Layer Errors Associated with the NT Function
269
Table 14.5 Conditions Handled as Unsupported Requests (UR) by the NT Function
271
Table 14.6 Conditions Handled as Unexpected Completion (UC) by the NT Function
272
NTB Inter-Partition Error Propagation
273
Figure 14.13 Basic Non-Transparent PES12NT12G2 Configuration
273
Table 14.9 Error Logging at each Function for Poisoned TLP Example
278
Figure 14.16 Poisoned TLP Error Propagation Example
278
Figure 14.17 Example of Combined Transaction Layer Error Handling
280
Error Emulation Control in the NT Function
281
Non Transparent Operation Restrictions
282
DMA Controller
283
Overview
283
Base Address Registers
283
DMA Channel Functional Description
283
Data Transfer and Addressing
284
Figure 15.1 DMA Data Transfer
284
Figure 15.2 Linear Addressing
285
Figure 15.3 Linear Addressing Operations
285
Table 15.1 DMA Channel Addressing Parameters
286
Figure 15.4 DMA Channel Addressing
286
Table 15.2 Linear Addressing DMA Example
287
DMA Descriptors
288
Table 15.3 Constant Addressing DMA Example
288
Figure 15.5 Constant Addressing Example
288
Figure 15.6 DMA Descriptor List
288
Figure 15.7 General DMA Descriptor Format
289
Table 15.4 Stride Control DMA Descriptor Fields
290
Figure 15.8 Stride Control DMA Descriptor Format
290
Table 15.5 Data Transfer DMA Descriptor Fields
292
Figure 15.9 Data Transfer DMA Descriptor Format
292
Table 15.6 Immediate Data Transfer DMA Descriptor Fields
295
Figure 15.10 Immediate Data Transfer DMA Descriptor Format
295
DMA Descriptor Processing
297
Table 15.7 DMA Chaining Disabling
299
Figure 15.11 DMA Chaining Example
299
Table 15.8 DMA Channel Control (Dmacxctl) Register Action Summary
301
TLP Attribute and Traffic Class Control
302
Channel Interrupts
303
DMA Outstanding Requests
303
Descriptor Prefetching
304
DMA Request Rate Control
304
DMA Multicast
305
Figure 15.12 Path Taken by a TLP Emitted by the DMA When It Is Multicasted
306
Figure 15.13 Path Taken by a TLP Emitted by the DMA When It Is NT Multicasted
306
Virtual Channel (VC) Support
307
Access Control Services (ACS) Support
307
Table 15.9 Downstream Switch Port Interrupts
307
Table 15.10 ACS Checks Performed by the DMA Function
308
Table 15.11 TLP Types Affected by ACS Checks
308
Power Management
309
Bus Locking
309
ECRC Support
309
Error Handling
309
Figure 15.14 Example of ACS Peer-To-Peer Request Redirect Applied by the DMA Function
309
PCI Express Error Handling by the DMA Function
310
Table 15.12 PCI Express Errors Detected by the DMA Function's Transaction Layer
312
Table 15.13 Prioritization of Transaction Layer Errors
317
DMA Limitations and Usage Restrictions
318
Figure 15.15 DMA Function's Error Checking and Logging on a Received TLP
318
Switch Events
319
Overview
319
Link up
320
Figure 16.1 Switch Event Detection and Signaling Mechanism
320
Link down
321
Fundamental Reset
321
Hot Reset
321
Failover
321
Global Signals
322
Figure 16.2 Global Signaling Mechanism
322
Port AER Errors
323
Multicast
325
Transparent Multicast Operation
325
Addressing and Routing
325
Figure 17.1 Multicast Group Address Ranges
327
Figure 17.2 Multicast Group Address Region Determination
328
Usage Restrictions
330
Non-Transparent Multicast Operation
330
NT Multicast Configuration
331
Figure 17.3 Transparent and Non-Transparent Multicast
331
NT Multicast TLP Determination
332
NT Multicast TLP Routing
332
NT Multicast Egress Processing
333
Usage Restrictions
335
Temperature Sensor
337
Overview
337
Register Organization
339
Overview
339
Table 19.1 Global Address Space Layout
339
Partial-Byte Access to Word and Dword Registers
341
Configuration Register Side-Effects
341
Address Maps
342
PCI-To-PCI Bridge Function Registers
342
Figure 19.1 PCI-To-PCI Bridge Configuration Space Organization
343
Table 19.2 PCI-To-PCI Bridge Function Configuration Space Registers
344
Table 19.3 Default Linkage of Capability Structures for a PCI-To-PCI Bridge Function in the Upstream Switch Port Mode
348
Table 19.4 Default Linkage of Capability Structures for a PCI-To-PCI Bridge Function in a Downstream or Unattached Port
348
Proprietary Port-Specific Registers in the PCI-To-PCI Bridge Function
349
Figure 19.2 Proprietary Port Specific Register Organization
350
Table 19.5 Proprietary Port Specific Registers
351
NT Function Registers
352
Figure 19.3 NT Function Configuration Space Organization
353
Table 19.6 NT Function Registers
354
Table 19.7 Default Linkage of Capability Structures for the NT Function When Operating as Function 0 of the Port
359
Table 19.8 Default Linkage of Capability Structures for the NT Function When Operating as Function 1 of the Port
360
DMA Function Registers
361
Table 19.9 Default Linkage of Capability Structures for the DMA Function
361
Figure 19.4 DMA Function Configuration Space Organization
362
Table 19.10 DMA Function Registers
363
Switch Configuration and Status Registers
366
Figure 19.5 Switch Configuration and Status Space Organization
367
Table 19.11 Switch Configuration and Status
368
PCI-To-PCI Bridge Registers
377
PCI Express Capability Structure
389
PCI Power Management Capability Structure
411
Subsystem ID and Subsystem Vendor ID
414
Extended Configuration Space Access Registers
415
Advanced Error Reporting (AER) Extended Capability
416
Device Serial Number Extended Capability
426
PCI Express Virtual Channel Capability
427
ACS Extended Capability
430
Multicast Extended Capability
435
Proprietary Port Specific Registers
441
Upstream PCI-To-PCI Bridge Interrupt and Signaling
441
Port AER Mask Register
443
Port Slot Control
445
Internal Error Control and Status Registers
447
Physical Layer Control and Status Registers
464
Request Metering
469
WRR Port Arbitration Counts
470
Non-Transparent Multicast Overlay
473
AER Error Emulation
475
Global Address Space Access Registers
478
NT Endpoint Registers
481
Type 0 Configuration Header Registers
481
PCI Power Management Capability Structure
508
Message Signaled Interrupt Capability Structure
509
Subsystem ID and Subsystem Vendor ID
511
Extended Configuration Space Access Registers
511
Device Serial Number Extended Capability
523
PCI Express Virtual Channel Capability
524
Multicast Extended Capability
530
NT Registers
533
NT Control & Status
533
NT Interrupt and Signaling
534
Internal Error Reporting Masks
536
Doorbell Registers
542
Message Registers
543
BAR Configuration
545
Mapping Table
564
Lookup Table
567
AER Error Emulation
568
Punch-Through Configuration Registers
571
NT Multicast
573
DMA Function Registers
575
Type 0 Configuration Header Registers
575
PCI Express Capability Structure
583
PCI Power Management Capability Structure
595
Message Signaled Interrupt Capability Structure
597
Extended Configuration Space Access Registers
598
ACS Extended Capability
610
DMA Registers
612
BAR Configuration
612
DMA AER Error Emulation
613
Internal Error Reporting Masks
615
Global Address Space Access Registers
631
Switch Configuration and Status Registers
633
Internal Switch Timers
636
Failover Capability Registers
644
Protection
646
Switch Event Registers
651
Global Doorbells and Message Registers
654
Serdes Control and Status Registers
655
General Purpose I/O Registers
662
Hot-Plug and Smbus Interface Registers
664
Temperature Sensor Registers
675
JTAG Boundary Scan
681
Introduction
681
Test Access Point
681
Signal Definitions
681
Figure 25.1 Diagram of the JTAG Logic
681
Table 25.1 JTAG Pin Descriptions
682
Figure 25.2 State Diagram of the TAP Controller
682
Table 25.2 Boundary Scan Chain
683
Test Data Register (DR)
685
Boundary Scan Registers
685
Figure 25.3 Diagram of Observe-Only Input Cell
686
Figure 25.4 Diagram of Output Cell
686
Instruction Register (IR)
687
Figure 25.5 Diagram of Bidirectional Cell
687
Extest
688
Sample/Preload
688
Bypass
688
Table 25.3 Instructions Supported by the JTAG Boundary Scan
688
Clamp
689
Idcode
689
Validate
689
Extest_Train
689
Table 25.4 System Controller Device Identification Register
689
Figure 25.6 Device ID Register Format
689
Extest_Pulse
690
Reserved
690
Usage Considerations
690
Usage Models
691
Introduction
691
Boot-Time Stack Reconfiguration
691
Figure 26.1 PES24NT24AG2 with One X8 Port and Sixteen X1 Ports
691
Port Clocking Configuration
692
Boot-Time Switch Partitioning
693
Figure 26.2 PES24NT6AG2 with Ports Operating in Different Clock Modes
693
Switch Partitioning Via Serial EEPROM
694
Figure 26.3 PES16NT8BG2 with Two Partitions Configured Via Serial EEPROM
694
Switch Partitioning Via PCI Express Configuration Requests
695
Figure 26.4 PES16NT8BG2 with Two Partitions Configured Via a Switch Manager Root Complex
696
Dynamic Port and Partition Reconfiguration
698
I/O Load Balancing: Downstream Port Migration
698
Figure 26.5 I/O Load Balancing Example: Initial Switch Configuration
698
Non-Transparent Bridge (NTB) Usage Models
701
PES12NT12G2 as a Multiprocessor System Interconnect
701
Figure 26.6 I/O Load Balancing Example: Switch Configuration after Port Migration
701
Figure 26.7 Multiprocessor System Interconnection Using the PES12NT12G2
702
NT Crosslink & NT Punch-Through
705
Figure 26.8 System Configuration Immediately after Switch Fundamental Reset
705
Figure 26.9 System Configuration after Serial EEPROM Initialization
706
DMA Usage Models
707
High-Performance Multiprocessor System
707
Figure 26.10 System Configuration Immediately after Switch Fundamental Reset
708
Figure 26.11 Target System Configuration
709
Immediate Descriptor Usage
710
Failover
710
Active / Passive Failover Configuration
710
Figure 26.12 Active/Passive System Configuration before Failover Event
711
Active / Active Failover Configuration
713
Figure 26.13 Active/Passive System Configuration after Failover Event
713
Figure 26.14 Active/Active System Configuration before Failover Event
714
Figure 26.15 Active/Active System Configuration before Failover Event
716
Failover with Two Crosslinked PES12NT12G2 Switches
717
Figure 26.16 High Availability System Configuration with Redundant PCI Express Switches
717
Figure 26.17 System Configuration after RC2 Modifies Port 8 in Switch #2
719
NT Multicasting
720
Figure 26.18 System Configuration after RC2 Modifies Port 8 in Switch #1
720
Figure 26.19 PES12NT12G2 with Port 0 Configured in NT Function with DMA Mode and Ports 2, 8, and 16 in NT Function Mode
721
Figure 26.20 PES12NT12G2 with Port 0 Configured in NT Function with DMA Mode and Ports 2, 8, and 16 in NT Function Mode
722

Renesas IDT 89HPES12NT12G2 Hardware Design Manual (23 pages)

IDT PCI Express 24-Port 32-Lane Gen 2 Switch

Brand: Renesas | Category: Switch | Size: 0 MB

Lane Reversal
5
Local Port Clocked Mode
12
Smbus Interfaces
14
Initialization from Serial EEPROM
15
Switch Partitioning
19
Reference Documents
21
Revision History
21
Corporate Headquarters
22
Contact Information
22

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Renesas IDT 89HPES12NT12G2 Hardware Design Manual (23 pages)

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