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IDT Hot-Plug and Hot-Swap
Notes
PES48H12G2 User Manual
If a hot-plug event occurs while a downstream port is in D3hot and the corresponding interrupt is
enabled, the port will generate an interrupt if the corresponding event's status bit is set in the PCIESCTL is
set and the state of the port is transitioned from D3
Legacy System Hot-Plug Support
Some systems require support for operating systems that lack PCIe hot-plug support. PES48H12G2
supports these systems by providing a General Purpose Event (GPEN) output as a GPIO alternate function
that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot-plug.
– Since the PES48H12G2 only supports a single GPEN output signal, the GPEN signal is associ-
ated with partition 0. Partitions other than 0 do not support this feature.
Associated with each downstream port's hot-plug controller is a bit in the General Purpose Event
Control (GPECTL) register. When this bit is set, the corresponding PCIe base 2.0 hot plug event notification
mechanisms are disabled for that port and INTx, MSI and PME events will not be generated by that port
due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN signal.
GPEN is a GPIO alternate function. The GPIO pin will not be asserted when GPEN is asserted unless it
is configured to operate as an alternate function. Whenever a port signals a hot-plug event through asser-
tion of the GPEN signal, the corresponding port's status bit in the General Purpose Event Status (GPESTS)
register is set. A bit in the GPESTS register can only be set if the corresponding port's hot plug controller is
configured to signal hot-plug events using the general purpose event (GPEN) signal assertion mechanism.
The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to
use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI
and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities,
status and control registers operate as normal and all other hot-plug functionality associated with the port
remains unchanged. INTx, MSI and PME events from other sources are also unaffected.
The enhanced hot-plug signalling mechanism supported by the PES48H12G2 is graphically illustrated
in Figure 10.6. This figure provides a conceptual summary of the enhanced hot-plug signalling mechanism
in the form of a pseudo logic diagram. Logic gates in this diagram are intended for conveying general
concepts, and not for direct implementation.
to D0 without a reset.
hot
10 - 7
April 5, 2013
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