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IDT Power Management
Notes
PES48H12G2 User Manual
Power Budgeting Capability
PES48H12G2 contains the mechanisms necessary to implement the PCI-Express power budgeting
enhanced capability. However, by default, these mechanisms are not enabled. To enable the power
budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in
one of the other enhanced capabilities should be initialized to point to the power budgeting capability. The
Next Pointer (NXTPTR) of the power budgeting capability should be adjusted if necessary.
Each PES48H12G2 Function contains a power budgeting capability structure. This structure consists of
the four power budgeting capability registers defined in the PCI Express 2.0 base specification and eight
general purpose read-write registers.
The Power Budgeting Capabilities (PWRBCAP) register contains the PCI-Express enhanced capability
header for the power budgeting capability. By default, this register has an initial read-only value of zero. To
enable the power budgeting capability, this register should be initialized via the serial EEPROM. The Power
Budgeting Data Value [7:0] (PWRBDV[7:0]) registers are used to hold the power budgeting information for
that Function in a particular operating condition.
The PWRBDV registers may be read and written when the Power Budgeting Data Value Unlock
(PWRBDVUL) bit is set in the Switch Control (SWCTL) register. When the PWRBDVUL bit is cleared, these
registers are read-only and writes to these registers are ignored. To enable the power budgeting capability,
the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM.
11 - 4
April 5, 2013
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