Advanced Error Reporting (Aer) Enhanced Capability - Renesas IDT 89HPES48H12G2 User Manual

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field Name
11:8
31:12 Reserved
ECFGDATA - Extended Configuration Space Access Data (0x0FC)
Bit
Field Name
31:0

Advanced Error Reporting (AER) Enhanced Capability

AERCAP - AER Capabilities (0x100)
Bit
Field Name
15:0
19:16 CAPVER
31:20 NXTPTR
PES48H12G2 User Manual
Field Default
Type
Value
EREG RW 0x0
RO 0x0
Field Default
Type
Value
DATA RW 0x0
Field Default
Type
Value
CAPID RO 0x1
RO 0x1
RWL Refer to sec-
tion Capabil-
ity Structures
on page 15-3.
Description
Extended Register Number. This field selects the extended con-
figuration register number as defined by Section 7.2.2 of the PCI
Express Base Specification, Rev. 2.0.
The value of this register must not be programmed to point to the
address offset of this register (i.e., 0xF8) or the ECFGDATA regis-
ter (i.e., 0xFC). Violation of this rule produces undefined results.
Also, the value of this register must not be programmed to point to
the address offset of the global address space registers (GASAA-
DDR and GASADATA). Violation of this rule produces undefined
results.
Reserved field.
Description
Configuration Data. A read from this field will return the configura-
tion space register value pointed to by the ECFGADDR register. A
write to this field will update the contents of the configuration space
register pointed to by the ECFGADDR register with the value writ-
ten. For both reads and writes, the byte enables correspond to
those used to access this field.
SMBus reads of this field return a value of zero and SMBus writes
have no effect.
Description
Capability ID. The value of 0x1 indicates an advanced error
reporting capability structure.
Capability Version. The value of 0x1. indicates compatibility with
version 1 of the specification.
Next Pointer. Next capability pointer. The value of 0x0 terminates
the list.
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