IDT PES48H12G2 Device Overview
Notes
PES48H12G2 User Manual
Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus
and System inputs should be tied off to appropriate levels. This is especially critical for unused control
signal inputs which, if left floating, could adversely affect operation. Also, floating pins can cause a
slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally,
No Connection pins should not be connected.
Function
Pin Name
PCI Express
PE00RN[3:0]
Interface
PE00RP[3:0]
PE00TN[3:0]
PE00TP[3:0]
PE01RN[3:0]
PE01RP[3:0]
PE01TN[3:0]
PE01TP[3:0]
PE02RN[3:0]
PE02RP[3:0]
PE02TN[3:0]
PE02TP[3:0]
PE03RN[3:0]
PE03RP[3:0]
PE03TN[3:0]
PE03TP[3:0]
PE04RN[3:0]
PE04RP[3:0]
PE04TN[3:0]
PE04TP[3:0]
PE05RN[3:0]
PE05RP[3:0]
PE05TN[3:0]
PE05TP[3:0]
PE06RN[3:0]
PE06RP[3:0]
PE06TN[3:0]
PE06TP[3:0]
PE07RN[3:0]
PE07RP[3:0]
PE07TN[3:0]
PE07TP[3:0]
PE08RN[3:0]
PE08RP[3:0]
PE08TN[3:0]
Type
Buffer
Type
I
PCIe
Serial Link
2
differential
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
Table 1.11 Pin Characteristics (Part 1 of 3)
1 - 13
I/O
Internal
Notes
1
Resistor
April 5, 2013