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IDT Reset and Initialization
Notes
PES48H12G2 User Manual
Registers and fields designated as Sticky (Sticky) take on their initial value as a result of the following
resets. Other resets have no effect on registers and fields with this designation.
– Switch Fundamental Reset
– Partition Fundamental Reset
All fields designated and Read Write when Unlocked (RWL) are implicitly SWSticky. Their value is
preserved across all resets except a switch fundamental reset.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 5.2 is sampled during a switch funda-
mental reset. Since the boot configuration vector is only sampled during a switch fundamental reset, the
value of signals that make up the boot configuration vector is ignored and their state outside of a switch
fundamental reset sequence has no effect on the operation of the device.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require more complex initialization. This initialization may be performed by an external
SMBus device via the slave SMBus interface or may be performed automatically via the serial EEPROM.
See Chapter 13, SMBus Interfaces, for a description of the slave SMBus interface and serial EEPROM
operation.
As noted in table Table 5.2, some of the initial values specified by the boot configuration vector may be
overridden by software, serial EEPROM, or an external SMBus device. The state of all of the boot configu-
ration signals in Table 5.2 sampled during a switch fundamental reset may be determined from the Boot
Configuration Status (BCVSTS) register.
Signal
Overridden
GCLKFSEL
CLKMODE[2:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1213MERGEN
Table 5.2 Boot Configuration Vector Signals (Part 1 of 2)
May Be
N
Global Clock Frequency Select.
These pins specifies the frequency of the GCLKP and
GCLKN signals.
Y
Clock Mode.
These pins specify the clocking mode used by switch ports.
See Table 4.1 for a definition of the encoding of these signals.
The value of these signals may be overridden by modifying
the Port Clocking Mode (PCLKMODE) register.
N
Ports 0 and 1 Merge.
This pin specifies whether ports 0 and 1 are merged.
N
Ports 2 and 3 Merge.
This pin specifies whether ports 2 and 3 are merged.
N
Ports 4 and 5 Merge.
This pin specifies whether ports 4 and 5 are merged.
N
Ports 6 and 7 Merge.
This pin specifies whether ports 6 and 7 are merged.
N
Ports 8 and 9 Merge.
This pin specifies whether ports 8 and 9 are merged.
N
Ports 12 and 13 Merge.
This pin specifies whether ports 12 and 13 are merged.
5 - 2
Name/Description
April 5, 2013
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