Renesas IDT Tsi572 Manuals

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Renesas IDT Tsi572 User Manual

Renesas IDT Tsi572 User Manual (510 pages)

Brand: Renesas | Category: Switch | Size: 3 MB

Table of Contents

Table of Contents
3
About this Document
17
Scope
17
Document Conventions
17
Revision History
18
Functional Overview
21
Overview
21
Typical Applications
22
Figure 1: Block Diagram
22
Figure 2: Processor Farm Mezzanine Diagram
23
Figure 3: Switch Carrier Blade Diagram
23
Features
24
Serial Rapidio Interface
26
Features
26
Transaction Flow Overview
26
Maintenance Requests
27
Control Symbols
27
Multicast Engine
27
Multicast Operation
27
Features
27
Serial Rapidio Electrical Interface
28
Figure 4: Tsi572 MAC Block Diagram
29
Internal Switching Fabric (ISF)
30
Internal Register Bus (AHB)
30
I 2 C Interface
30
JTAG Interface
32
Serial Rapidio Interface
35
Overview
35
Features
35
Transaction Flow Overview
36
Maintenance Requests
36
Control Symbols
36
Transaction Flow
37
Lookup Tables
37
Filling the Lookup Tables
38
Figure 5: LUT Mode of Operation
39
LUT Modes
40
Flat Mode
40
Figure 6: Flat Mode Routing
41
Figure 7: Flat Mode LUT Configuration Example
42
Hierarchical Mode
44
Mixed Mode of Operation
45
Lookup Table Parity
45
Figure 8: Hierarchical Mode
45
Lookup Table Error Summary
46
Table 1: Error Summary
46
Lookup Table Entry States
47
Table 2: Lookup Table States
47
Maintenance Packets
49
Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi572 Responses
49
Multicast Event Control Symbols
51
MCS Reception
51
Generating an MCS
52
Restrictions
52
Reset Control Symbol Processing
53
Data Integrity Checking
53
Packet Data Integrity Checking
53
Control Symbol Data Integrity Checking
53
Error Management
53
Software Assisted Error Recovery
54
Hot Insertion and Hot Extraction
55
Hot Insertion
56
Hot Extraction
57
Hot Extraction System Notification
58
Loss of Lane Synchronization
58
Figure 9: LOLS Silent Period
59
Dead Link Timer
60
Lane Sync Timer
60
Serial Rapidio Electrical Interface
61
Overview
61
Figure 10: Tsi572 MAC Block Diagram
62
Port Numbering
63
Port Configuration
63
Port Aggregation: 1X and 4X Modes
63
Figure 11: Port Configuration
63
Table 4: Tsi572 Port Numbering
63
1X + 1X Configuration
64
Configuration
65
Clocking
65
Changing the Clock Speed
66
Table 5: Reference Clock Frequency and Supported Serial Rapidio Data Rates
66
Changing the Clock Speed through I
67
Port Power down
67
Default Configurations on Power down
68
Special Conditions for Port 0 Power down
68
Power-Down Options
69
Configuration and Operation through Power-Down
69
Table 6: Serial Port Power-Down Procedure
69
Port Lanes
70
Lane Synchronization and Alignment
70
Lane Swapping
71
Table 7: Lane Sequence
71
Programmable Transmit and Receive Equalization
72
Transmit Drive Level and Equalization
72
Receive Equalization
73
Figure 12: Drive Strength and Equalization Waveform
73
Port Loopback Testing
74
Figure 13: Tsi572 Loopbacks
74
Digital Equipment Loopback
75
Logical Line Loopback
75
Bit Error Rate Testing (BERT)
75
BERT Pattern Generator
75
Table 8: Patterns Supported by Generator
75
BERT Pattern Matcher and Error Counter
77
Fixed Pattern-Based BERT
77
Table 9: Patterns Supported by Matcher
77
Using PRBS Scripts for the Transmitters and Receivers
78
Internal Switching Fabric
79
Overview
79
Functional Behavior
80
Figure 14: ISF Block Diagram
80
Transfer Modes
81
Arbitration for Egress Port
82
Strict Priority Arbitration
82
Figure 15: Egress Arbitration: Weighted Round Robin and Strict Priority
82
Weighted Round Robin (WRR) Arbitration
83
Figure 16: Weighted Round Robin Arbiter Per Priority Group
83
Table 10: Sample Register Settings for WRR in a Given Priority Group (WRR_EN=1)
84
Packet Queuing
85
Output Queuing on the Egress Port
85
Figure 17: Ingress and Egress Packet Queues in Tsi572
85
Table 11: Examples of Use of Watermarks
87
Input Queue for the ISF Port
88
Input Arbitration
89
Input Queuing Model for the Multicast Work Queue
93
Input Queuing Model for the Broadcast Buffer
94
Output Queuing Model for Multicast
94
ISF Bandwidth
94
Multicast
97
Overview
97
Multicast Operation
97
Features
97
Multicast Operation with Multiple Tsi57X Switches
98
Figure 18: Multicast Operation - Option 1
98
Multicast Terminology
99
Figure 19: Multicast Operation - Option 2
99
Table 12: Multicast Terminology
99
Multicast Behavior Overview
100
Multicast Work Queue
101
Broadcast Buffers
101
Figure 20: Multicast Packet Flow in the Tsi572
102
Multicast Group Tables
104
Configuring Basic Associations
106
Figure 21: Relationship Representation
106
Configuring Multicast Masks
107
Figure 22: Completed Tables at the End of Configuration
108
Configuring Multicast Masks Using the IDT Specific Registers
110
Arbitration for Multicast Engine Ingress Port
111
Figure 23: IDT-Specific Multicast Mask Configuration
111
Error Management of Multicast Packets
112
Packet TEA
112
Multicast Packet Stomping
112
Figure 24: Arbitration Algorithm for Multicast Port
112
Multicast Maximum Latency Timer
113
Silent Discard of Packets
114
Port-Writes and Multicast
114
Port Reset
114
Event Notification
115
Overview
115
Event Summary
116
Table 13: Tsi572 Events
116
Error Rate Thresholds
120
Maintaining Packet Flow
121
Error Stopped State Recovery
122
Error Stopped States
122
Link Error Clearing and Recovery
123
Figure 25: Control Symbol Format
124
Event Capture
125
Table 14: Error Rate Error Events
126
Port-Write Notifications
127
Destination ID
128
Payload
128
Servicing Port-Writes
129
Table 15: Port Write Packet Data Payload - Error Reporting
129
Port-Writes and Hot Insertion/Hot Extraction Notification
130
Port-Writes and Multicast
130
Interrupt Notifications
130
Figure 26: Rapidio Block Interrupt and Port Write Hierarchy
131
Int_B Signal
132
Global Interrupt Status Register and Interrupt Handling
132
Table 16: Port X Error and Status Register Status
133
Interrupt Notification and Port-Writes
134
Reset Control Symbol and Interrupt Handling
134
I 2 C Interface
135
Overview
135
Protocol Overview
137
Block Diagram
138
Figure 27: I 2 C Block Diagram
139
Figure 28: I 2 C Reference Diagram
140
Tsi572 as I 2 C Master
141
Figure 29: Software-Initiated Master Transactions
142
Example EEPROM Read and Write
143
Master Clock Generation
143
Master Bus Arbitration
144
Master External Device Addressing
144
Master Peripheral Addressing
144
Master Data Transactions
145
Tsi572 as I 2 C Slave
145
Slave Clock Stretching
147
Figure 30: Transaction Protocols for Tsi572 as Slave
147
Slave Device Addressing
148
Slave Peripheral Addressing
148
External I C Register Map
149
Slave Write Data Transactions
150
Slave Read Data Transactions
151
Slave Internal Register Accesses
151
Slave Access Examples
152
Resetting the I 2 C Slave Interface
155
Mailboxes
155
Figure 31: I 2 C Mailbox Operation
156
Table 17: Externally Visible I
156
Incoming Mailbox
157
Outgoing Mailbox
157
Smbus Support
157
Unsupported Smbus Features
158
Smbus Protocol Support
158
Figure 32: Smbus Protocol Support
159
Smbus Alert Response Protocol Support
160
Boot Load Sequence
160
Figure 33: Smbus Alert Response Protocol
160
Figure 34: Boot Load Sequence
161
Idle Detect
162
EEPROM Reset Sequence
162
Wait for Bus Idle
162
EEPROM Device Detection
163
Loading Register Data from EEPROM
163
Chaining
164
EEPROM Data Format
164
Table 18: Format for Boot Loadable EEPROM
165
Table 19: Sample EEPROM Loading Two Registers
165
I2C Boot Time
166
Table 20: Sample EEPROM with Chaining
166
Accelerating Boot Load
167
Error Handling
168
Table 21: I 2 C Error Handling
168
Interrupt Handling
170
Figure 35: I 2 C Interrupt Generation
170
Events Versus Interrupts
171
Figure 36: I 2 C Event and Interrupt Logic
172
Timeouts
173
Table 22: I 2 C Interrupt to Events Mapping
173
Figure 37: I 2 C Timeout Periods
176
Bus Timing
177
Figure 38: I 2 C Bus Timing Diagrams
178
Start/Restart Condition Setup and Hold
179
Stop Condition Setup
179
I2C_SD Setup and Hold
179
I2C_SCLK Nominal and Minimum Periods
180
Idle Detect Period
180
Performance
181
Overview
181
Throughput
181
Latency
181
Performance Monitoring
182
Figure 39: Latency Illustration
182
Table 23: Performance Monitoring Parameters
183
Traffic Efficiency
184
Throughput
184
Bottleneck Detection
185
Congestion Detection
185
Resetting Performance Registers
185
Configuring the Tsi572 for Performance Measurements
186
Clock Speeds
186
Tsi572 ISF Arbitration Settings
186
Tsi572 Rapidio Transmission Scheduler Settings
187
Tsi572 Rapidio Buffer Watermark Selection Settings
187
Port-To-Port Performance Characteristics
187
Port-To-Port Packet Latency Performance
187
Packet Throughput Performance
188
Table 24: 4X/1X Latency Numbers under no Congestion
188
Multicast Performance
189
Congestion Detection and Management
190
Table 25: 4X/1X Multicast Latency Numbers under no Congestion
190
Figure 40: Congestion and Detection Flowchart
191
Congestion Registers
192
Figure 41: Congestion Example
194
JTAG Interface
195
Overview
195
JTAG Device Identification Number
196
JTAG Register Access Details
196
Format
196
Figure 42: Register Access from JTAG - Serial Data in
196
Write Access to Registers from the JTAG Interface
197
Read Access to Registers from the JTAG Interface
197
Clocks, Resets and Power-Up Options
199
Clocks
199
Clocking Architecture
200
Serdes Clocks
201
Reference Clocks
201
Table 26: Tsi572 Input Reference Clocks
201
Clock Domains
202
Clock Gating
202
Table 27: Tsi572 Clock Domains
202
Resets
203
Device Reset
203
Per-Port Reset
205
Generating a Rapidio Reset Request to a Peer Device
205
JTAG Reset
205
Power-Up Options
206
Power-Up Option Signals
206
Table 28: Power-Up Options Signals
207
Default Port Speed
208
Port Power-Up and Power-Down
208
Port Width Override
208
Signals
209
Overview
209
Table 29: Signal Types
209
Endian Ordering
210
Port Numbering
210
Table 30: Tsi572 Port Numbering
210
Signal Groupings
211
Table 31: Tsi572 Signal Descriptions
212
Pinlist and Ballmap
220
Serial Rapidio Registers
221
Overview
221
Table 32: Address Rules
221
Reserved Register Addresses and Fields
222
Table 33: Register Access Types
222
Port Numbering
223
Conventions
223
Table 34: Tsi572 Port Numbering
223
Register Map
224
Table 35: Register Map Overview
224
Table 36: Register Map
225
Rapidio Logical Layer and Transport Layer Registers
234
Rapidio Device Identity CAR
235
Rapidio Device Information CAR
236
Rapidio Assembly Identity CAR
237
Rapidio Assembly Information CAR
238
Rapidio Processing Element Features CAR
239
Rapidio Switch Port Information CAR
241
Rapidio Source Operation CAR
242
Rapidio Switch Multicast Support CAR
244
Rapidio Route LUT Size CAR
245
Rapidio Switch Multicast Information CAR
246
Rapidio Host Base Device ID Lock CSR
247
Rapidio Component Tag CSR
248
Rapidio Route Configuration Destid CSR
249
Rapidio Route Configuration Output Port CSR
250
Rapidio Route LUT Attributes (Default Port) CSR
251
Rapidio Multicast Mask Configuration Register
252
Rapidio Multicast Destid Configuration Register
254
Rapidio Multicast Destid Association Register
255
Rapidio Physical Layer Registers
257
Table 37: Physical Interface Register Offsets
257
Rapidio 1X or 4X Switch Port Maintenance Block Header
258
Rapidio Switch Port Link Timeout Control CSR
259
Rapidio Switch Port General Control CSR
260
Rapidio Serial Port X Link Maintenance Request CSR
261
Rapidio Serial Port X Link Maintenance Response CSR
263
Rapidio Serial Port X Local Ackid Status CSR
264
Rapidio Port X Error and Status CSR
266
Rapidio Serial Port X Control CSR
269
Rapidio Error Management Extension Registers
273
Table 38: Error Management Registers
273
Port Behavior When Error Rate Failed Threshold Is Reached
274
Table 39: STOP_FAIL_EN and DROP_EN Setting
274
Rapidio Error Reporting Block Header
275
Rapidio Logical and Transport Layer Error Detect CSR
276
Rapidio Logical and Transport Layer Error Enable CSR
277
Rapidio Logical and Transport Layer Address Capture CSR
278
Rapidio Logical and Transport Layer Device ID Capture CSR
279
Rapidio Logical and Transport Layer Control Capture CSR
280
Rapidio Port-Write Target Device ID CSR
281
Rapidio Port X Error Detect CSR
282
Rapidio Port X Error Rate Enable CSR
285
Rapidio Port X Error Capture Attributes CSR and Debug 0
287
Table 40: ERR_TYPE Values
287
Rapidio Port X Packet and Control Symbol Error Capture CSR 0 and Debug 1
289
Rapidio Port X Packet Error Capture CSR 1 and Debug 2
290
Rapidio Port X Packet Error Capture CSR 2 and Debug 3
290
Rapidio Port X Packet Error Capture CSR 3 and Debug 4
291
Rapidio Port X Error Rate CSR
292
Rapidio Port X Error Rate Threshold CSR
294
IDT-Specific Rapidio Registers
295
Table 41: IDT-Specific Broadcast Rapidio Registers
295
Table 42: IDT-Specific Per-Port Performance Registers
296
Rapidio Port X Discovery Timer
297
Rapidio Port X Mode CSR
298
Rapidio Port X Multicast-Event Control Symbol and Reset Control Symbol Interrupt CSR
300
Rapidio Port X Rapidio Watermarks
301
Rapidio Port X Route Config Destid CSR
302
Rapidio Port X Route Config Output Port CSR
303
Rapidio Port X Local Routing LUT Base CSR
304
Rapidio Multicast Write ID X Register
305
Rapidio Multicast Write Mask X Register
306
Rapidio Port X Control Independent Register
307
Rapidio Port X Send Multicast-Event Control Symbol Register
310
Rapidio Port X LUT Parity Error Info CSR
311
Rapidio Port X Control Symbol Transmit
313
Rapidio Port X Interrupt Status Register
314
Rapidio Port X Interrupt Generate Register
317
IDT-Specific Performance Registers
319
Table 43: IDT-Specific Per-Port Performance Registers
319
Rapidio Port X Performance Statistics Counter 0 and 1 Control Register
320
Rapidio Port X Performance Statistics Counter 2 and 3 Control Register
324
Rapidio Port X Performance Statistics Counter 4 and 5 Control Register
328
Rapidio Port X Performance Statistics Counter 0 Register
332
Rapidio Port X Performance Statistics Counter 1 Register
333
Rapidio Port X Performance Statistics Counter 2 Register
334
Rapidio Port X Performance Statistics Counter 3 Register
335
Rapidio Port X Performance Statistics Counter 4 Register
336
Rapidio Port X Performance Statistics Counter 5 Register
337
Rapidio Port X Transmitter Output Queue Depth Threshold Register
338
Rapidio Port X Transmitter Output Queue Congestion Status Register
340
Rapidio Port X Transmitter Output Queue Congestion Period Register
342
Rapidio Port X Receiver Input Queue Depth Threshold Register
343
Rapidio Port X Receiver Input Queue Congestion Status Register
345
Rapidio Port X Receiver Input Queue Congestion Period Register
347
Rapidio Port X Reordering Counter Register
348
Serial Port Electrical Layer Registers
349
Table 44: IDT-Specific Rapidio Registers
349
Table 45: Serial Port Electrical Layer Registers
349
BYPASS_INIT Functionality
350
SRIO MAC X Serdes Configuration Channel 0
351
SRIO MAC X Serdes Configuration Channel 1
354
SRIO MAC X Serdes Configuration Channel 2
356
SRIO MAC X Serdes Configuration Channel 3
358
SRIO MAC X Serdes Configuration Global
360
Table 46: TX_LVL Values
361
Table 47: AC JTAG Level Programmed by ACJT_LVL[4:0]
362
SRIO MAC X Serdes Configuration Globalb
364
SRIO MAC X Digital Loopback and Clock Selection Register
365
Internal Switching Fabric (ISF) Registers
368
Fabric Control Register
368
Fabric Interrupt Status Register
370
Rapidio Broadcast Buffer Maximum Latency Expired Error Register
371
Rapidio Broadcast Buffer Maximum Latency Expired Override
372
Utility Unit Registers
373
Global Interrupt Status Register
373
Global Interrupt Enable Register
375
Rapidio Port-Write Timeout Control Register
376
Rapidio Port Write Outstanding Request Register
377
MCES Pin Control Register
378
Multicast Registers
379
Rapidio Multicast Register Version CSR
379
Rapidio Multicast Maximum Latency Counter CSR
380
Rapidio Port X ISF Watermarks
381
Port X Prefer Unicast and Multicast Packet Prio 0 Register
382
Port X Prefer Unicast and Multicast Packet Prio 1 Register
383
Port X Prefer Unicast and Multicast Packet Prio 2 Register
384
Port X Prefer Unicast and Multicast Packet Prio 3 Register
385
Serdes Per Lane Register
386
Table 48: Serdes Register Map
386
Serdes Lane 0 Pattern Generator Control Register
387
Serdes Lane 1 Pattern Generator Control Register
388
Serdes Lane 2 Pattern Generator Control Register
389
Serdes Lane 3 Pattern Generator Control Register
390
Serdes Lane 0 Pattern Matcher Control Register
391
Serdes Lane 1 Pattern Matcher Control Register
392
Serdes Lane 2 Pattern Matcher Control Register
393
Serdes Lane 3 Pattern Matcher Control Register
394
Serdes Lane 0 Frequency and Phase Value Register
395
Serdes Lane 1 Frequency and Phase Value Register
396
Serdes Lane 2 Frequency and Phase Value Register
397
Serdes Lane 3 Frequency and Phase Value Register
398
I2C Registers
399
Register Map
399
Table 49: I 2 C Register Map
399
Register Descriptions
402
I 2 C Device ID Register
402
I 2 C Reset Register
403
I 2 C Master Configuration Register
404
I 2 C Master Control Register
406
Table 50: Master Operation Sequence
408
I 2 C Master Receive Data Register
409
I 2 C Master Transmit Data Register
410
I 2 C Access Status Register
411
I 2 C Interrupt Status Register
414
I 2 C Interrupt Enable Register
417
I 2 C Interrupt Set Register
419
I 2 C Slave Configuration Register
421
I 2 C Boot Control Register
424
Externally Visible I C Internal Write Address Register
428
Externally Visible I C Internal Write Data Register
429
Externally Visible I C Internal Read Address Register
430
Externally Visible I
430
Internal Read Data Register
431
Externally Visible I
431
Slave Access Status Register
432
Externally Visible I C Internal Access Control Register
434
Externally Visible I
434
Status Register
436
Externally Visible I
436
Enable Register
439
Externally Visible I C Outgoing Mailbox Register
442
Externally Visible I C Incoming Mailbox Register
443
I 2 C Event and Event Snapshot Registers
444
I 2 C New Event Register
448
I 2 C Enable Event Register
451
I 2 C Time Period Divider Register
454
I 2 C Start Condition Setup/Hold Timing Register
455
I 2 C Stop/Idle Timing Register
456
I2C_SD Setup and Hold Timing Register
457
I2C_SCLK High and Low Timing Register
458
I2C_SCLK Minimum High and Low Timing Register
459
I2C_SCLK Low and Arbitration Timeout Register
460
I 2 C Byte/Transaction Timeout Register
461
I 2 C Boot and Diagnostic Timer
462
I 2 C Boot Load Diagnostic Progress Register
463
I 2 C Boot Load Diagnostic Configuration Register
464
Serial Rapidio Protocol Overview
465
Protocol
465
Packets
465
Control Symbols
466
Physical Layer
466
PCS Layer
466
PMA Layer
466
Physical Protocol
466
Table 51: Special Characters and Encoding
467
Table 52: Control Symbol Construction
468
Clocking
471
Line Rate Support
471
Table 53: Tsi572 Supported Line Rates
471
Register Requirements Using 125 Mhz S_CLK for a 3.125 Gbps Link Rate
472
P_CLK Programming
475
Rapidio Specifications Directly Affected by Changes in the P_CLK Frequency
475
Table 54: Timer Values with P_CLK and TVAL Variations
476
Table 55: Timer Values with DISCOVERY_TIMER and P_CLK Variations
477
IDT Specific Timers
478
Table 56: Timer Values with P_CLK and DLT_THRESH Variations
478
I 2 C Interface and Timers
479
Other Performance Factors
485
PRBS Scripts
487
Tsi572_Start_Prbs_All.txt Script
487
Tsi572_Framer_Disable.txt Script
489
Tsi572_Sync_Prbs_All.txt Script
490
Tsi572_Read_Prbs_All.txt Script
493
EEPROM Scripts
497
Script
497
Index
505

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