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IDT Switch Core
Notes
PES48H12G2 User Manual
To facilitate testing of software error handlers, any bit in the IERRORSTS register may be set by writing
a one to the corresponding bit position in the Internal Error Test (IERRORTST) register. Once a bit is set in
the ERRORSTS register, it is processed as though the actual error occurred (e.g., reported by AER).
Switch Time-Outs
The switch core discards any TLP that reaches the head of an IFB or EFB queue and is more than 64
seconds old. This includes posted, non-posted, completion and inserted TLPs. If during processing of a
TLP with broadcast routing a switch core time-out occurs, then the switch core will abort processing of the
TLP. This may result in the broadcast TLP being transmitted on some but not all downstream pots.
Memory SECDED ECC Protection
PCI Express provides reliable hop-by-hop communication between interconnected devices, such as
roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level
retransmission protocol. While this mechanism provides reliable communication between interconnected
devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an
optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC)
computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the
ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it
is an optional PCI Express feature and has not been implemented in many North-Bridges and endpoints. In
addition, the ECRC mechanism does not cover variant fields within a TLP.
Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is
desired that detects errors that occur within a PCI Express switch.
The PES48H12G2 protects all memories (i.e., both data and control structures) with a Single Error
Correction with Double Error Detection (SECDED) Error Correcting Code (ECC). The objective of this
memory protection is to prevent silent data corruption. Single bit errors are automatically corrected and
optionally reported while double bit errors are optionally reported.
Double bit errors are uncorrectable memory errors that may compromise the integrity of control and data
structures. Detection of a double bit error may result in further modification of one or more memory bits in
the data quantity in which the error was detected (i.e., single bit error correction is not disabled when a
double bit error is detected and a double bit error may result in one or more single bit corrections).
Associated with each port are five memories: IFB control, IFB data, and EFB control, EFB data, and
Replay Buffer Control. Each port contains memory error control and status registers that are used to
manage memory errors associated with that port.
When a single or double bit error is detected in a memory, the status bit corresponding to the memory in
which the error was detected is set in the Internal Error Reporting Status (IERRORSTS) register.
A double bit error detected by a memory associated with TLP data (i.e., IFB or EFB data) results in the
TLP being nullified when it reaches the DL layer of an egress port. The TLP is nullified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by a link partner are
discarded. Although the TLP is nullified, flow control credits associated with the egress port may not be
correctly updated. Thus, double bit errors could result in a flow control credit leak.
The DL layer never replays a TLP with a sequence number different from that initially used. If a double
bit error is detected during a DL layer replay, then all TLPs in the replay buffer are flushed.
If a double bit error is detected by an internal memory in a TLP that targets a function in the switch (e.g.,
a configuration read or write request to the PCI-to-PCI bridge function), then the TLP is discarded.
End-to-End Data Path Parity Protection
In addition to memory ECC protection, the PES48H12G2 supports end-to-end data path parity protec-
tion. Data flowing into the PES48H12G2 is protected by the LCRC. Within the Data Link (DL) layer of the
switch ingress port, the LCRC is checked and a 32-bit DWord even parity is computed on the received TLP
data. If an LCRC error is detected at this point, the link level retransmission protocol is used to recover from
the error by forcing a retransmission by the link partner.
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April 5, 2013
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