Figure 13.2 Single Double Word Initialization Sequence Format; Figure 13.3 Sequential Double Word Initialization Sequence Format - Renesas IDT 89HPES48H12G2 User Manual

IDT SMBus Interfaces
Notes
PES48H12G2 User Manual
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6

Figure 13.2 Single Double Word Initialization Sequence Format

The second type of configuration block is the sequential double word initialization sequence. It is similar
to a single double word initialization sequence except that it contains a double word count that allows
multiple sequential double words to be initialized in one configuration block.
A sequential double word initialization sequence consists of four required fields and one to 65535
double word initialization data fields. The format of a sequential double word initialization sequence is
shown in Figure 13.3. The TYPE field indicates the type of the configuration block. For sequential double
word initialization sequences, this value is always 0x1. The SYSADDR field contains the starting double
word system address to be initialized. The NUMDW field specifies the number of double words initialized by
the configuration block. This is followed by the number of DATA fields specified in the NUMDW field.
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 4n+5
Byte 4n+ 6
Byte 4n+7
Byte 4n+8

Figure 13.3 Sequential Double Word Initialization Sequence Format

Bit Bit Bit Bit Bit
7 6 5 4 3
TYPE Reserved
0x0 (must be zero)
SYSADDR[9:2]
SYSADDR[18:10]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
Bit Bit Bit Bit Bit
7 6 5 4 3
TYPE Reserved
0x1 (must be zero)
SYSADDR9:2]
SYSADDR[18:10]
NUMDW[7:0]
NUMDW[15:8]
DATA0[7:0]
DATA0[15:8]
DATA0[23:16]
DATA0[31:24]
DATAn[7:0]
DATAn[15:8]
DATAn[23:16]
DATAn[31:24]
13 - 3
Bit Bit Bit
2 1 0
Bit Bit Bit
2 1 0
April 5, 2013