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IDT Link Operation
Notes
PES48H12G2 User Manual
L1 state from its link partner. If the link partner acknowledges the transition, then the L1 state is entered.
Otherwise, L0s entry is attempted
when all of the conditions listed below are met:
– L1 ASPM is enabled via the port's PCIELCTL register.
– All of the downstream ports in the partition which are not in a low power state (i.e., D3) and whose
link is not down are in the L1 state.
– The port has no TLPs pending for transmission.
The port's replay-buffer is empty.
– The port has no DLLPs pending for transmission.
– The port's receiver is idle (i.e., no TLPs or DLLPs are received) for the amount of time specified
above.
– The port has accumulated enough flow-control header and data credits to transmit the largest
possible packet of each type (i.e., posted, non-posted, or completion).
L1 Exit Conditions
The L1 exit conditions depend on the port's operational state. A port configured in 'Upstream Switch
Port' mode initiates exit from L1 when any of the conditions listed below are met:
– The port has a TLP scheduled for transmission.
– A downstream port in the switch partition has initiated exit from L1.
The latency between the downstream port's initiated exit from L1 and the upstream port's initi-
ated exit from L1 must not exceed 1 µs.
A port configured in 'Downstream Switch Port' mode initiates exit from L1 when any of the conditions
listed below are met:
– The port has a TLP scheduled for transmission.
– The upstream port in the switch partition has initiated exit from L1.
The latency between the upstream port's initiated exit from L1 and the downstream port's initi-
ated exit from L1 must not exceed 1 µs.
L1 ASPM Entry Rejection Timer
When enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, PES48H12G2
downstream ports respond to link partner requests to enter the L1 ASPM state. In order to enter the L1
ASPM link state, a downstream device (i.e., endpoint) sends continuous PM_Active_State_Request_L1
DLLPs to its link partner (i.e., a downstream switch port). This process continues until the downstream
device receives an acceptance or rejection from its link partner.
A PES48H12G2 downstream port can choose to accept or reject the request, depending on a variety of
conditions (refer to section L1 Entry Conditions on page 7-12). When accepting a request, the
PES48H12G2 downstream port sends continuous PM_Request_Ack DLLPs until the downstream device
receives these and sends an electrical idle ordered set, effectively placing the link in L1 state.
When rejecting a request, the PES48H12G2 downstream port sends a single PM_Active_State_Nak
TLP. The downstream device, upon reception of this TLP, should place its transmitter into the L0s state, and
exit this state prior to sending a new L1 ASPM entry request. Optionally, the downstream device may keep
the link in L0 state, in which case it must wait at least 10 µs before sending a new L1 ASPM entry request.
1.
L0s entry is subject to the rules specified in section L0s ASPM on page 7-12.
1
A port configured in 'Upstream Switch Port' mode initiates L1 entry
7 - 13
April 5, 2013
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