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Renesas IDT 89HPES16T7 User Manual

Renesas IDT 89HPES16T7 User Manual

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IDT
89HPES16T7
™
PCI Express® Switch
User Manual
April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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  • Page 1 ® 89HPES16T7 ™ PCI Express® Switch User Manual April 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES16T7, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan- dard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

  • Page 4: Numeric Representations

    Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

  • Page 5: Register Terminology

    Notes The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2. bit 31 bit 0 Address of Bytes within Words: Big Endian...

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Peer-to-Peer Transactions......................3-8 Bus Locking ............................ 3-9 Port Interrupts ..........................3-10 Legacy Interrupt Emulation......................3-11 Standard PCIe Error Detection and Handling................3-12 Physical Layer Errors ......................3-12 Data Link Layer Errors......................3-12 Transaction Layer Errors ...................... 3-13 Routing Errors ........................
  • Page 9 IDT Table of Contents Hot-Plug and Hot-Swap Notes Introduction ............................. 8-1 Hot-Plug I/O Expander ......................8-4 Hot-Plug Interrupts and Wake-up ................... 8-4 Legacy System Hot-Plug Support ..................8-4 Hot-Swap ............................8-6 Configuration Registers Introduction ............................. 9-1 Upstream Port (Port 0) ......................9-3 Downstream Ports (Ports 1 through 6) ...................
  • Page 10 IDT Table of Contents Notes PES16T7 User Manual April 10, 2008...
  • Page 11 List of Tables ® Table 1.1 PES16T7 Device ID......................1-5 Notes Table 1.2 PES16T7 Revision ID ......................1-5 Table 1.3 PCI Express Interface Pins....................1-6 Table 1.4 SMBus Interface Pins ......................1-7 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins.........................1-8 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes Table 10.4 System Controller Device Identification Register .............. 10-8 PES16T7 User Manual April 10, 2008...
  • Page 13 List of Figures ® Figure 1.1 PES16T7 Architectural Block Diagram ................1-3 Notes Figure 1.2 PES16T7 Logic Diagram ....................1-4 Figure 1.3 All Ports Unmerged Configuration ...................1-13 Figure 1.4 Some Ports Merged Configuration ...................1-13 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
  • Page 14 IDT List of Figures Notes Figure 10.4 Diagram of Output Cell ....................10-5 Figure 10.5 Diagram of Bidirectional Cell ....................10-6 Figure 10.6 Device ID Register Format ....................10-8 PES16T7 User Manual viii April 10, 2008...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-41 AERCTL - AER Control (0x118)......................9-42 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCICMD - PCI Command Register (0x004)....................9-12 PCIECAP - PCI Express Capability (0x040) ...................9-21 PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-22 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-32 PCIEDCTL - PCI Express Device Control (0x048)..................9-23 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-32 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-24 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................9-32...
  • Page 17 IDT Register List Notes SWPESTS - Switch Parity Error Status (0x744) ..................9-63 SWSTS - Switch Status (0x400) ......................9-50 SWTOCNT - Switch Time-Out Count (0x75C) ..................9-65 SWTOCTL - Switch Time-Out Control (0x750) ..................9-64 SWTORCTL - Switch Time-Out Reporting Control (0x758) ..............9-64 SWTOSTS - Switch Time-Out Status (0x754) ..................9-64 SWTOTSCTL - Switch Time-Out Time-Stamp Control (0x760) ..............9-66 SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) .............9-62...
  • Page 18 IDT Register List Notes PES16T7 User Manual April 10, 2008...

  • Page 19: Pes16T7 Device Overview

    Chapter 1 PES16T7 Device Overview ® Introduction Notes The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI Express switching solutions. The PES16T7 is a 16-lane, 7-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage and communications/networking.
  • Page 20 IDT PES16T7 Device Overview Notes Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O –...

  • Page 21: System Diagrams

    IDT PES16T7 Device Overview System Diagrams Switch Core D-Bus Bus Decoupler D-Bus U-Bus U-Bus Arbiter Queue Arbiter GPIO Controller Master SMBus Interface Slave Input Input Input Input Input Input Input Input SMBus Frame Frame Frame Frame Frame Frame Frame Frame Interface Buffer Buffer...

  • Page 22: Logic Diagram

    IDT PES16T7 Device Overview Logic Diagram PEREFCLKP PE0TP[0] Reference PEREFCLKN PCI Express PE0TN[0] Clocks Switch REFCLKM SerDes Output PE0TP[3] Port 0 PE0RP[0] PE0TN[3] PCI Express PE0RN[0] Switch PE1TP[0] SerDes Input PCI Express PE0RP[3] PE1TN[0] Port 0 Switch PE0RN[3] SerDes Output PE1TP[3] Port 1 PE1TN[3]...

  • Page 23: System Identification

    IDT PES16T7 Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES16T7 device ID is shown in Table 1.1. PCIe Device Device ID 0x802D Table 1.1 PES16T7 Device ID...

  • Page 24: Pin Description

    IDT PES16T7 Device Overview Pin Description Notes The following tables lists the functions of the pins provided on the PES16T7. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 25: Table 1.4 Smbus Interface Pins

    IDT PES16T7 Device Overview Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed.

  • Page 26: Table 1.6 System Pins

    IDT PES16T7 Device Overview Notes Signal Type Name/Description GPIO[6] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: Reserved Alternate function pin type: Input Alternate function: Reserved GPIO[7] General Purpose I/O. This pin can be configured as a general purpose I/O pin.

  • Page 27: Table 1.7 Test Pins

    IDT PES16T7 Device Overview Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside PES16T7 and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES16T7 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 28: Table 1.8 Power And Ground Pins

    IDT PES16T7 Device Overview Notes Signal Type Name/Description CORE Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator.

  • Page 29: Pin Characteristics

    IDT PES16T7 Device Overview Pin Characteristics Notes Note: Some input pads of the PES16T7 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

  • Page 30: Port Configuration

    IDT PES16T7 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor SMBus MSMBADDR[4:1] LVTTL Input pull-up MSMBCLK MSMBDAT SSMBADDR[5,3:1] Input pull-up SSMBCLK SSMBDAT General Pur- GPIO[11:0] LVTTL High Drive pull-up pose I/O System Pins CCLKDS LVTTL Input pull-up CCLKUS pull-up...
  • Page 31 IDT PES16T7 Device Overview • This renders the registers in port y’s configuration space inaccessible to the root. Notes – All registers associated with port y become inaccessible via the SMBus. Reading or writing an inaccessible register has an undefined effect. •...
  • Page 32 IDT PES16T7 Device Overview Notes PES16T7 User Manual 1 - 14 April 10, 2008...

  • Page 33: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES16T7 has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.
  • Page 34 IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES16T7 Port 0 Root Complex Port 6 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock) Port 1 PES16T7 Port 0...

  • Page 35: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES16T7 Port 0 Root Complex Port 6 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Clock Generator Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES16T7 during a fundamental reset when PERSTN is negated.

  • Page 36: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside PES16T7 and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES16T7 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 37 IDT Clocking, Reset, and Initialization Clock Operation Notes The following reset sequence is executed. 1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN). 2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental reset is the result of a one being written to the FRST bit in the SWCTL register).

  • Page 38: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes The PES16T7 provides a reset output signal for each downstream port implemented as a GPIO alter- nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated.

  • Page 39: Upstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes 6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES16T7 registers are updated.

  • Page 40: Downstream Port Reset Outputs

    IDT Clocking, Reset, and Initialization Clock Operation Notes When a downstream secondary bus reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted 2. All TLPs received from corresponding downstream port and queued in the PES16T7 are discarded. 3.

  • Page 41: Power Good Controlled Reset Output

    IDT Clocking, Reset, and Initialization Clock Operation Power Good Controlled Reset Output Notes As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply.
  • Page 42 IDT Clocking, Reset, and Initialization Clock Operation Notes PES16T7 User Manual 2 - 10 April 10, 2008...

  • Page 43: Theory Of Operation

    Chapter 3 Theory of Operation ® Introduction Notes An architectural block diagram of the PES16T7 is shown in Figure 1.1 in Chapter 1. The PES16T7 contains seven x4 ports labeled port 0 through port 6. Port 0 is always the upstream port and ports one through six are always downstream ports.

  • Page 44: Data Paths

    IDT Theory of Operation Notes Associated with each port in the data link layer is a shared output and replay buffer. That is, the buffer is partitioned into two sections with a section dedicated to each x4 port in bifurcated mode. This buffer contains TLPs that have been transmitted but have not been acknowledged by the link partner.

  • Page 45: Store-And-Forward Vs. Cut-Through Switching And Latency

    IDT Theory of Operation Notes continuous TLP manner (i.e. the data is not TDMed) regardless of the operating mode of the stack. If the stack is in bifurcated mode, data is read from the output and replay buffer by the data link layer in a TDM manner.

  • Page 46: Transaction Routing

    IDT Theory of Operation Bus Decoupler Queue U-Bus D-Bus Upstream Downstream Downstream Downstream Downstream Downstream Downstream Port Port Port Port Port Port Port Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath In addition to transactions between the upstream port and downstream port and peer-to-peer transactions, the switch core is responsible for routing of transactions which are destined to the same stack on which the TLP was received.

  • Page 47: Transaction Reordering

    IDT Theory of Operation Notes A summary of TLP types that use the above routing methods is provided in Table 3.5. Routing Method TLP Type Using Routing Method Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, TCfgRd, TCfgWr, Cpl, CpdD, CplLk, CplDLk, Msg, MsgD Imlicit Routing - Route to Root...

  • Page 48: Scheduling And Port Arbitration

    IDT Theory of Operation Notes Logical Queue Head Non-Posted Completion Posted Valid Ordering Valid Valid NP > P > CP.ro NP > CP > P CP > P > NP CP > NP > P Table 3.6 IFB Transaction Ordering (Part 2 of 2) When two logical TLP types are destined to the same egress port from the same ingress port, the rela- tive TLP type age is used to order the TLPs (i.e., the older one is allowed to progress first).
  • Page 49 IDT Theory of Operation Notes Dword TLPs, the maximum overhead introduced by the U-Bus arbiter is one clock cycle per TLP. U-Bus arbitration logically occurs in two stages. In the first stage, a transfer class is selected, and in the second stage, the actual transfer within that transfer class is selected.

  • Page 50: Peer-To-Peer Transactions

    IDT Theory of Operation Notes Transaction Class Arbitration Weighted Round Robin Upstream Downstream Downstream Peer Upstream Peer Self Self Upstream route-to-self Downstream route-to- Upstream port arbiter Peer-to-peer transfer selects transfer using selected using fair arbi- selected (only choice) self selected using fair hardwired fixed round tration.

  • Page 51: Bus Locking

    IDT Theory of Operation Notes Some systems view peer-to-peer transactions as a potential security vulnerability since this capability allows one endpoint to modify the state of another without protection checks. When the Disable Peer-to- Peer (DP2P) bit is set in the Switch Control (SWCTL) register, all PES16T7 peer-to-peer transactions are disabled.

  • Page 52: Port Interrupts

    IDT Theory of Operation Notes The behavior of the switch is undefined when: – a PCIe configuration space register is read while the switch is locked – any transaction other than a MWr, MRdLk, and Unlock message is received on the upstream port when the switch is locked –...

  • Page 53: Legacy Interrupt Emulation

    IDT Theory of Operation Notes EN bit in INTXD bit Unmasked MSICAP in PCICMD Actions Interrupt Register Register Asserted MSI message generated Assert_INTA message request generated to switch core None Negated None Deassert_INTA message request generated to switch core None Table 3.7 Downstream Port Interrupts Legacy Interrupt Emulation The PES16T7 supports legacy PCI INTx emulation.

  • Page 54: Standard Pcie Error Detection And Handling

    IDT Theory of Operation Notes Upstream Port Interrupt (Port 0) INTA INTB INTC INTD Downstream Port Port 1 INTD Port 1 INTA Port 1 INTB Port 1 INTC Interrupt Port 2 INTC Port 2 INTD Port 2 INTA Port 2 INTB Port 3 INTB Port 3 INTC Port 3 INTD...

  • Page 55: Transaction Layer Errors

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section TLP ending in ENDB with LCRC that does not 3.5.3.1 TLP discarded match inverted calculated LCRC TLP received with incorrect LCRC 3.5.3.1 Correctable error processing TLP received with sequence number not equal 3.5.3.1 Correctable error processing to NEXT_RCV_SEQ and this is not a duplicate...

  • Page 56: Table 3.12 Ingress Malformed Tlp Error Checks

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section Completer abort 2.3.1 Not applicable. The PES16T7 Completion time-out never generates non-posted transactions as a requester. Unexpected completion 2.3.2 For the non-advisory cases: non- fatal error processing. Advisory cases: correctable error processing.

  • Page 57: Routing Errors

    IDT Theory of Operation Notes TLP Type Error Check I/O read or write request LENGTH = 1 (doubleword) TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000 Configuration read or write request LENGTH = 1 (doubleword) TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000 Message Requests...

  • Page 58: Switch Specific Error Detection And Handling

    IDT Theory of Operation Notes Address Routed TLPs – TLPs whose address decoding indicates they are to route back to the port on which they were received. – TLPs received on the upstream port that match the upstream port’s address range but which do not match a downstream port’s address range (i.e., TLPs that do not route through the PES16T7).

  • Page 59: End-To-End Parity Checking

    IDT Theory of Operation Notes Whenever a TLP is discarded by a port due to a switch time-out, a bit corresponding to the type of TLP that was discarded is set in port’s Switch Time-Out Status (SWTOSTS) register. In addition, a saturating count field corresponding to the type of TLP that was discarded is incremented in the port’s Switch Time- Out Count (SWTOCNT) register.

  • Page 60: Tlp Processing

    IDT Theory of Operation Notes All internal memories used to store TLP data within the PES16T7 are Dword even parity protected. Parity errors in these memories are propagated and reported using the end-to-end parity protection mecha- nism. The End-to-End Parity Error Reporting (EEPE) field in the Switch Parity Error Reporting Control (SWPERCTL) register controls the manner in which end-to-end parity errors are reported.

  • Page 61: Port 1 Performance Characteristics

    IDT Theory of Operation Port 1 Performance Characteristics Notes As shown in Figure 1.1, port zero and port one share the same bifurcating PCIe stack. Since port zero is an upstream port and port one is a downstream port, the performance characteristics of port one differs from that of the other downstream ports.
  • Page 62 IDT Theory of Operation Notes PES16T7 User Manual 3 - 20 April 10, 2008...

  • Page 63: Link Operation

    Chapter 4 Link Operation ® Introduction Notes The PES16T7 contains seven x4 ports which may be merged in pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES16T7 supports automatic polarity inversion as required by the PCIe specification.
  • Page 64 IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES16T7 PES16T7 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal PExRP[0] lane 0 PExRP[0]...
  • Page 65 IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES16T7 PES16T7 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal PExRP[0] PExRP[0] lane 0...
  • Page 66 IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES16T7 PES16T7 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal (a) x4 Port without lane reversal PExRP[0] PExRP[0]...

  • Page 67: Link Retraining

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES16T7 PES16T7 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5] lane 5 PExRP[6] lane 1...

  • Page 68: Link Down

    IDT Link Operation Link Down Notes When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR).

  • Page 69: Active State Power Management

    IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.6 PES16T7 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is independent of power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.

  • Page 70: Link Status

    IDT Link Operation Link Status Notes Associated with each port is a Port Link Up (PxLINKUP) status output and a Port Activity (PxACTIVE) status output. These outputs are provided on I/O Expander 4. See section I/O Expanders on page 6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.

  • Page 71: General Purpose I/O

    Chapter 5 General Purpose I/O ® Introduction Notes The PES16T7 has 12 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 72: Gpio Pin Configured As An Input

    IDT General Purpose I/O Notes GPIOFUNC GPIOCFG Pin Function GPIO input GPIO output don’t care Alternate function Table 5.2 GPIO Pin Configuration GPIO Pin Configured as an Input When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register.

  • Page 73: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES16T7 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES16T7, allowing every register in the device to be read or written by an external SMBus master.

  • Page 74: Master Smbus Interface

    IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses. Thus, multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.

  • Page 75: Table 6.2 Pes16T7 Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.2 PES16T7 Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.
  • Page 76 IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.3 Sequential Double Word Initialization Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end...

  • Page 77: Table 6.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence . The correct result should always be 0xFF (i.e., all ones). Checksum checking may be disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the SMBus Control (SMBUSCTL) register.

  • Page 78: I/O Expanders

    IDT SMBus Interfaces Notes Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results. SMBus errors may occur when accessing the serial EEPROM. If an error occurs, it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access.
  • Page 79 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES16T7 to I/O expander zero, one and three (i.e., the ones that contain hot-plug signals). – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 80 IDT SMBus Interfaces Notes An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initialized to its default value. When this occurs, the internal PES16T7 state of the hot-plug signals is in conflict with the state of I/O expander hot-plug output signals.

  • Page 81: Table 6.5 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes 2. If the I/O expanders are initialized via serial EEPROM, then the data value for output signals during the SMBus initialization sequence will correspond to those at the time the SMBus transactions are initiated. It is not possible to toggle SMBus I/O expander outputs by modifying data values during serial EEPROM initialization.

  • Page 82: Table 6.6 I/O Expander 1 Signals

    IDT SMBus Interfaces Notes I/O Expander 1 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P3APN Port 3 attention push button input 1 (I/O-0.1) P3PDN Port 3 presence detect input 2 (I/O-0.2) P3PFN Port 3 power fault input 3 (I/O-0.3) P3MRLN Port 3 manually-operated retention latch (MRL) input...

  • Page 83: Table 6.8 I/O Expander 3 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 8 (I/O-1.0) Unused 9 (I/O-1.1) P1PWRGDN Port 1 power good input 10 (I/O-1.2) P2PWRGDN Port 2 power good input 11 (I/O-1.3) P3PWRGDN Port 3 power good input 12 (I/O-1.4) P4PWRGDN Port 4 power good input 13 (I/O-1.5) P5PWRGDN...

  • Page 84: Slave Smbus Interface

    IDT SMBus Interfaces Notes I/O Expander 4 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P0LINKUP Port 0 link up status output 1 (I/O-0.1) P1LINKUP Port 1 link up status output 2 (I/O-0.2) P2LINKUP Port 2 link up status output 3 (I/O-0.3) P3LINKUP Port 3 link up status output...

  • Page 85: Smbus Transactions

    IDT SMBus Interfaces Notes Address Bit Address Bit Value SSMBADDR[5] Table 6.10 Slave SMBus Address When a Static Address is Selected SMBus Transactions The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. See the SMBus 2.0 specification for a detailed description of these transactions. –...

  • Page 86: Table 6.12 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Name Description FUNCTION This field encodes the type of SMBus operation. 0 - CSR register read or write operation 1 - Serial EEPROM read or write operation 2 through 7 - Reserved SIZE This field encodes the data size of the SMBus transaction. 0 - Byte 1 - Word 2 - Block...

  • Page 87: Table 6.13 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Name Description Position DATALM Data Lower Middle. Bits [15:8] of data doubleword. DATAUM Data Upper Middle. Bits [23:16] of data doubleword. DATAUU Data Upper. Bits [31:24] of data doubleword. Table 6.12 CSR Register Read or Write Operation Byte Sequence (Part 2 of 2) The format of the CMD field is shown in Figure 6.6 and described in Table 6.13.

  • Page 88: Table 6.14 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Name Description Position CCODE Command Code. Slave Command Code field described in Table 6.11. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses to not contain this field. The byte count field indi- cates the number of bytes following the byte count field when performing a write or setting up for a read.
  • Page 89 IDT SMBus Interfaces Notes Bit Field Name Type Description NAERR No Acknowledge Error. This bit is set if an unexpected NACK is observed during a master SMBus transaction when accessing the serial EEPROM. This bit has the same function as the NAERR bit in the SMBUSSTS reg- ister.
  • Page 90 IDT SMBus Interfaces Notes PES16T7 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES16T7 Slave CCODE (PES16T7 not ready with data) SMBus Address START,END PES16T7 Slave CCODE PES16T7 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address ADDRL ADDRU DATA...
  • Page 91 IDT SMBus Interfaces Notes PES16T7 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES16T7 Slave CCODE ADDRU SMBus Address END, Byte CCODE PES16T7 Slave (PES16T7 not ready with data) START,Word SMBus Address PES16T7 Slave CCODE SMBus Address START,Word PES16T7 Slave CMD (status) ADDRL SMBus Address...
  • Page 92 IDT SMBus Interfaces Notes PES16T7 User Manual 6 - 20 April 10, 2008...

  • Page 93: Power Management

    Chapter 7 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES16T7 is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 94: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the state.

  • Page 95: Power Budgeting Capability

    IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES16T7 receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES16T7 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 96 IDT Power Management Notes PES16T7 User Manual 7 - 4 April 10, 2008...

  • Page 97: Notes

    Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES16T7 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
  • Page 98 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES16T7 Port 1 Port 2 PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES16T7 Master SMBus Port 1 Port 2 SMBus I/O...

  • Page 99: Table 8.1 Downstream Port Hot-Plug Signals

    IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES16T7 in an application involving an add-in card hot-plugged into a downstream slot. Associated with each downstream port in the PES16T7 is a hot- plug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capa- bilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).

  • Page 100: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes The default value of hot-plug registers following a hot or fundamental reset may be configured via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result of serial EEPROM initialization.
  • Page 101 IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.

  • Page 102: Hot-Swap

    IDT Hot-Plug and Hot-Swap Hot-Swap Notes The PES16T7 is hot-swap capable and meets the following requirements: – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.). – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

  • Page 103: Configuration Registers

    Chapter 9 Configuration Registers ® Introduction Notes Each software-visible register in the PES16T7 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES16T7 that cannot be accessed by the root. Each software- visible register in the PES16T7 has a system address.
  • Page 104 IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting Enhanced Capability Switch Control 0x400...

  • Page 105: Upstream Port (Port 0)

    IDT Configuration Registers Upstream Port (Port 0) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 106 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 107 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-42 0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 9-42 0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page...
  • Page 108 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword P0_PWRBDV3 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x310 Dword P0_PWRBDV4 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x314 Dword P0_PWRBDV5 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on...
  • Page 109 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page 9-63 0x74C Dword P0_SWPECNT SWPECNT - Switch Parity Error Count (0x74C) on page 9-63 0x750 Dword P0_SWTOCTL SWTOCTL - Switch Time-Out Control (0x750) on page 9-64 0x754...

  • Page 110: Downstream Ports (Ports 1 Through 6)

    IDT Configuration Registers Downstream Ports (Ports 1 through 6) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 111 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 112 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F0 Dword Px_SSIDSSVIDCA SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) on page 9-36 0x0F4 Dword Px_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on page 9-36 0x0F8 Word Px_ECFGADDR...
  • Page 113 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-50 0x28C Dword Px_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on page 9-50 0x300 Dword Px_PWRBDV0 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x304...

  • Page 114: Register Definitions

    IDT Configuration Registers Register Definitions Notes Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-5. DID - Device Identification Register (0x002) Field Default...
  • Page 115 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADSTEP Address Data Stepping. Not applicable. SERRE SERR Enable. Non-fatal and fatal errors detected by the bridge are reported to the Root Complex when this bit is set or the bits in the PCI Express Device Control register are set (see PCIEDCTL - PCI Express Device Control (0x048) on page 9-23).
  • Page 116 IDT Configuration Registers Notes Field Default Type Description Field Name Value RTAS Received Target Abort. Not applicable. RMAS Received Master Abort. Not applicable. RW1C Signalled System Error. This bit is set when the bridge sends a ERR_FATAL or ERR_NONFATAL message and the SERR Enable (SERRE) bit is set in the PCICMD regis- ter.
  • Page 117 IDT Configuration Registers Notes HDR - Header Type Register (0x00E) Field Default Type Description Field Name Value 0x01 Header Type. This value indicates a type 1 header with a single function bridge layout. BIST - Built-in Self Test Register (0x00F) Field Default Type...
  • Page 118 IDT Configuration Registers Notes SUBUSN - Subordinate Bus Number Register (0x01A) Field Default Type Description Field Name Value SUBUSN Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error. This bit is controlled by the Parity Error Response Enable bit in the Bridge Control register. If the Parity Response Enable bit is cleared, then this bit is never set.
  • Page 120 IDT Configuration Registers Notes PMBASE - Prefetchable Memory Base Register (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 -(prefmem32) 32-bit prefetchable memory addressing. 0x1 - (prefmem64) 64-bit prefetchable memory addressing. Reserved Reserved field.
  • Page 121 IDT Configuration Registers Notes IOBASEU - I/O Base Upper Register (0x030) Field Default Type Description Field Name Value 15:0 IOBASEU 0xFFFF I/O Address Base Upper. This field specifies the upper 16- bits of IOBASE. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 122 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot-plug by the downstream ports. This field should only be configured with values of 0x0 through 0x4.

  • Page 123: Pci Express Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
  • Page 124 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. The default value corresponds to 2048 bytes. Phantom Functions Supported.
  • Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:26 CSPLS Captured Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for the upstream port.
  • Page 126 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:12 MRRS Maximum Read Request Size. The bridge does not gener- ate transactions larger than 128 bytes and passes transac- tions through the bridge with the size unmodified. Therefore, this field has no functional effect on the behavior of the bridge.
  • Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum WDTH link width of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
  • Page 128 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 PORTNUM Port 0: 0x0 Port Number. This field indicates the PCI express port num- Port 1: 0x1 ber for the corresponding link. Port 2: 0x2 Port 3: 0x3 Port 4: 0x4 Port 5: 0x5 Port 6: 0x6...
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value HWAWDTH- Hardware Autonomous Width Disable. When set, this bit disables hardware from changing the link width for reasons other than attempting to correct for unreliable link operation by reducing the link width. This field is read-only zero in PCIe 1.1 mode.
  • Page 130 IDT Configuration Registers Notes Field Default Type Description Field Name Value LBWSTS RW1C Link Bandwidth Management Status. This bit is set to indicate that either of the following have occurred without the link transitioning through the DL_Down state. A link retraining initiated by setting the LRET bit in the PCIELCTL register has completed.
  • Page 131 IDT Configuration Registers Notes Field Default Type Description Field Name Value Hot-Plug Capable. This bit is set if the slot corresponding to the port is capable of supporting hot-plug operations. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSCE MRL Sensor Change Enable. This bit when set enables the generation of a Hot-Plug interrupt or wake-up event on a MRL sensor change event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
  • Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.
  • Page 134 IDT Configuration Registers Notes PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value 31:0 Reserved Reserved field. PCIEDCTL2 - PCI Express Device Control 2 (0x068) Field Default Type Description Field Name Value 15:0 Reserved Reserved field.

  • Page 135: Power Management Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:6 Reserved Reserved field. PCIELSTS2 - PCI Express Link Status 2 (0x072 Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) Field Default Type...
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value DEVSP Device Specific Initialization. The value of zero indicates that no device specific initialization is required. 24:22 AUXI AUX Current. not used D1 Support. This field indicates that the PES16T7 does not support D1.

  • Page 137: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 21:16 Reserved Reserved field. B2B3 B2/B3 Support. Does not apply to PCI Express. BPCCE Bus Power/Clock Control Enable. Does not apply to PCI Express. 31:24 DATA Data. This optional field is not implemented. Message Signaled Interrupt Capability Structure MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) Field...

  • Page 138: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) Field Default Type Description Field Name Value 31:0 UADDR Upper Message Address. This field specifies the upper portion of the DWORD address of the MSI memory write transaction. If the contents of this field are non-zero, then 64-bit address is used in the MSI memory write transaction.

  • Page 139: Extended Configuration Space Access Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:16 SSID Subsystem ID. This field identifies the add-in card or sub- system. SSID values are assigned by the vendor. Extended Configuration Space Access Registers ECFGADDR - Extended Configuration Space Access Address (0x0F8) Field Default Type...
  • Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:20 NXTPTR 0x200 Next Pointer. AERUES - AER Uncorrectable Error Status (0x104) Field Default Type Description Field Name Value UDEF RW1C Undefined. This bit is no longer used in this version of the Sticky specification.
  • Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value DLPERR Data Link Protocol Error Mask. When this bit is set, the Sticky corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 142 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specification. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported...
  • Page 143 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in Sticky the AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 144 IDT Configuration Registers Notes Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit Sticky in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.

  • Page 145: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 3rd doubleword of the Sticky TLP header that resulted in the first reported uncorrectable error.

  • Page 146: Pci Express Virtual Channel Capability

    IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capability structure. 19:16 CAPVER Capability Version.
  • Page 147 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. This field contains the offset of the VC arbitration table from the base address of the Vir- tual Channel Capability structure in double quad words (16 bytes).
  • Page 148 IDT Configuration Registers Notes Field Default Type Description Field Name Value Advanced Packet Switching. Not supported. RJST Reject Snoop Transactions. No supported for switch ports. 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field.
  • Page 149 IDT Configuration Registers Notes VCR0STS - VC Resource 0 Status (0x218) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PATS Port Arbitration Table Status. This bit indicates the coher- ency status of the port arbitration table associated with the VC resource and is valid only when the port arbitration table is used by the selected arbitration algorithm.
  • Page 150 IDT Configuration Registers Notes VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224) Field Default Type Description Field Name Value PHASE8 Phase 8. This field contains the port ID for the correspond- ing port arbitration period. PHASE9 Phase 9. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 151: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 11:8 PHASE26 Phase 26. This field contains the port ID for the correspond- ing port arbitration period. 15:12 PHASE27 Phase 27. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 152: Switch Control And Status Registers

    IDT Configuration Registers Notes PWRBD - Power Budgeting Data (0x288) Field Default Type Description Field Name Value 31:0 DATA Data. If the Data Value Select (DVSEL) field in the Power Budgeting Data Select register contains a value of zero through 31, then this field returns the contents of the corre- sponding Power Budgeting Data Value (PWRBDVx) regis- ter.
  • Page 153 IDT Configuration Registers Notes Field Default Type Description Field Name Value CCLKUS HWINIT Common Clock Upstream. This bit reflects the value of the CCLKUS signal sampled during the fundamental reset. MSMB- HWINIT Master SMBus Slow Mode. This bit reflects the value of the SMODE MSMBSMODE signal sampled during the fundamental reset.
  • Page 154 IDT Configuration Registers Notes Field Default Type Description Field Name Value RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except Sticky the SMBus interface remains in a reset state. In this state, registers in the device may be initialized by the slave SMBus interface.
  • Page 155 IDT Configuration Registers Notes HPCFGCTL - Hot-Plug Configuration Control (0x408) Field Default Type Description Field Name Value IPXAPN Invert Polarity of PxAPN. When this bit is set, the polarity Sticky of the PxAPN input is inverted in all ports. IPXPDN Invert Polarity of PxPDN.
  • Page 156 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 RST2PWR 0x14 Reset Negation. This field contains the delay from negation Sticky of a downstream port’s reset to disabling of a downstream port’s power in units of 10 mS. A value of zero corresponds to no delay.
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:16 Reserved Reserved field. SMBUSSTS - SMBus Status (0x424) Field Default Type Description Field Name Value Reserved Reserved field. SSMBADDR HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface.
  • Page 158 IDT Configuration Registers Notes SMBUSCTL - SMBus Control (0x428) Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock Sticky prescalar value used during master SMBus transactions. The prescalar clock period is equal to 32 ns multiplied by the value in this field.
  • Page 159 IDT Configuration Registers Notes EEPROMINTF - Serial EEPROM Interface (0x42C) Field Default Type Description Field Name Value 15:0 ADDR EEPROM Address. This field contains the byte address in the Serial EEPROM to be read or written. 23:16 DATA EEPROM Data. A write to this field will initiates a serial EEPROM read or write operation, as selected by the OP field, to the address specified in the ADDR field.
  • Page 160 IDT Configuration Registers Notes Field Default Type Description Field Name Value IOEXTM IO Expander Test Mode. Setting this bit puts the I/O expander interface into a test mode. In this test mode, I/O expander output signals generated by the PES16T7 core are ignored and values supplied to the I/O expander corre- spond to value written to the IOEDATA field.
  • Page 161 IDT Configuration Registers Notes IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438) Field Default Type Description Field Name Value Reserved Reserved field. IOE4ADDR I/O Expander 4 Address. This field contains the SMBus Sticky address assigned to I/O expander 4 on the master SMBus interface.
  • Page 162 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:7 Reserved Reserved field. GPESTS - General Purpose Event Status (0x454) Field Default Type Description Field Name Value Reserved Reserved field. P1GPES Port 1 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal.
  • Page 163 IDT Configuration Registers Notes UARBTC - U-Bus Arbiter Transfer Count (0x458) Field Default Type Description Field Name Value D2UTC 0x01 Downstream to Upstream Transfer Count. This field con- Sticky tains the downstream to upstream transfer count. The D2UCTC field in the UARBCTC register is set to this value after each arbitration period.

  • Page 164: Internal Switch Error Control And Status Registers

    IDT Configuration Registers Notes DARBCTC - D-Bus Arbiter Current Transfer Count (0x464) Field Default Type Description Field Name Value U2DCTC 0x01 Upstream to Downstream Current Transfer Count. This field contains the current upstream to downstream transfer count. 15:8 BDQ2DTC 0x01 Bus Decoupler Queue to Downstream Current Transfer Count.
  • Page 165 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 LENGTH Error Match Length. When the GBEEP bit is set, bad parity Sticky is generated for all double words in TLPs emitted to the switch core from this port (i.e., those received on the ingress port or generated by the stack) whose TLP header length field (i.e., bits seven through zero of byte zero of the TLP header) matches the value in this field.
  • Page 166 IDT Configuration Registers Notes SWTOCTL - Switch Time-Out Control (0x750) Field Default Type Description Field Name Value Enable Switch Time-outs. When this bit is set, switch time- Sticky outs for this port are enabled. In this mode, a TLP will be discarded if it has been in this port’s input queue for more than the specified switch core time-out limit.
  • Page 167 IDT Configuration Registers Notes Field Default Type Description Field Name Value NPTLPTO Non-Posted TLP Time-Out Reporting. This field controls Sticky the manner in which non-posted TLP time-outs are reported. A time-out is reported as specified in this field whenever the corresponding bit in the Switch Time-Out Status (SWTOSTS) register transitions from a zero to a one.
  • Page 168 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 CTLPTOC Completion TLP Time-Out Count. This field is incre- Sticky mented each time a TLP is discarded from the port’s IFB completion queue because of a time-out. This counter saturates at its maximum value. Reading this field causes it to be cleared.

  • Page 169: Jtag Boundary Scan

    Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES16T7: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 170: Table 10.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.

  • Page 171: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PE0RN[3:0] face PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0] PE5TP[3:0] PE6RN[3:0]...

  • Page 172: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell System Pins CCLKDS CCLKUS MSMBSMODE P01MERGEN PERSTN RSTHALT SWMODE[2:0] — EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — Table 10.2 Boundary Scan Chain (Part 2 of 2) I = Input, O = Output O = Observe, C = Control Test Data Register (DR)
  • Page 173 IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 10.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 10.4. EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell...

  • Page 174: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes The output enable cells are also output cells. The simplified logic is shown in Figure 10.5. shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 10.5 Diagram of Bidirectional Cell...

  • Page 175: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 176: Clamp

    IDT JTAG Boundary Scan Notes Therefore, instead of having to shift many times to get a value through the PES16T7, the user only needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
  • Page 177 IDT JTAG Boundary Scan Notes the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test- Logic-Reset controller state by continuously holding JTAG_TRST_N low and/or JTAG_TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it. PES16T7 User Manual 10 - 9 April 10, 2008...
  • Page 178 IDT JTAG Boundary Scan Notes PES16T7 User Manual 10 - 10 April 10, 2008...
  • Page 179 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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