Table 1.9 Test Pins - Renesas IDT 89HPES48H12G2 User Manual

IDT PES48H12G2 Device Overview
Notes
PES48H12G2 User Manual
Signal Type
P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low
internally.
When this pin is low, port 8 is merged with port 9 to form a single x8 port.
The Serdes lanes associated with port 9 become lanes 4 through 7 of port
8. Refer to section Port Merging on page 5-7 for details.
When this pin is high, port 8 and port 9 are not merged, and each operates
as a single x4 port.
P1213MERGEN I Port 12 and 13 Merge. P1213MERGEN is an active low signal. It is pulled
low internally.
When this pin is low, port 12 is merged with port13 to form a single x8 port.
The Serdes lanes associated with port 13 become lanes 4 through 7 of port
12. Refer to section Port Merging on page 5-7 for details.
When this pin is high, port 12 and port 13 are not merged, and each oper-
ates as a single x4 port.
PERSTN I Global Reset. Assertion of this signal resets all logic inside PES48H12G2.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES48H12G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48H12G2
switch operating mode. Note: These pins should be static and not change
following the negation of PERSTN.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-
0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-
0xA - Single partition with Serial EEPROM initialization and port 0 selected
0xB - Single partition with Serial EEPROM initialization and port 2 selected
0xC - Multi-partition
0xD - Multi-partition with Serial EEPROM initialization
0xE - Reserved
0xF - Reservedd
Table 1.8 System Pins (Part 2 of 2)
Signal Type
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
1 - 11
Name/Description
abled)
abled)
as the upstream port (port 2 disabled)
as the upstream port (port 0 disabled)
Name/Description
Table 1.9 Test Pins (Part 1 of 2)
April 5, 2013