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IDT Register Organization
Notes
PES48H12G2 User Manual
PCI-to-PCI Bridge Registers
This section outlines the configuration space associated with PCI-to-PCI bridges. These registers are
accessible as function 0 when the port is configured in the following modes.
– Upstream switch port
– Downstream switch port
These registers are always accessible regardless of the port mode using global address space access
registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM. Access to the Extended Configu-
ration Space Address Registers (ECFGADDR and ECFGDATA) located in the PCI-to-PCI Bridge function is
not allowed via the GASAADDR and GASADATA registers.
Figure 15.1 shows the organization of the configuration space.
– Registers with offsets between 0x000 and 0x0FF are associated with PCI configuration space.
– Registers with offsets between 0x100 and 0x3FF are associated with PCI Express extended
configuration space
– Registers with offsets between 0x400 and 0xFFF are associated with PCI Express extended
configuration space but are used to hold IDT proprietary port specific registers.
In order to facilitate access to the PCI Express extended configuration space by legacy PCI software,
the PCI-to-PCI bridge configuration space contains the Extended Configuration Space Access Address and
Data registers (ECFGADDR and ECFGDATA). Refer to the definition of these registers for further details.
Offset addresses for PCI-to-PCI bridge registers are listed in Table 15.4 and register definitions are
provided in Chapter 16. Registers in this address range are referenced as PxP2P_REGNAME where x
represents the PES48H12G2 port number and REGNAME represents the register name in Table 15.4.
Reading from a reserved address or region returns a value of zero. Writes to a reserved address
complete successfully but modify no data and have no other effect.
The port operating mode (e.g., upstream switch port or downstream switch port) determines the pres-
ence of configuration registers within the PCI-to-PCI bridge function's configuration space. For example,
the slot capability, slot control, and slot status registers are only present in the configuration space of a
bridge function in a downstream port.
Table 15.4 has two columns indicating the presence of each register within the PCI-to-PCI bridge func-
tion's space depending on the port operating mode. Column 'US' refers to a port in upstream switch mode,
and column 'DS' refers to a port in downstream switch mode. A mark of 'N' in the column indicates that the
corresponding register is not present in the configuration space. Otherwise, the register is present in the
configuration space. Registers that are not present in the configuration space are considered reserved
when the port operates in the corresponding operating mode.
Capability Structures
The PCI-to-PCI bridge function contains a number of PCI capability structures and PCI Express
extended capability structures. Following a fundamental reset, some of these capabilities are linked by
default and visible to software while others need to be explicitly linked to be made visible (e.g., via firmware,
serial EEPROM, or SMBus). Table 15.2 lists PCI Express capability structures and their default linkage (i.e.,
the default value of each capability's Next Pointer (NXTPTR) field). The default linkage is dependent on a
port's operating mode. A value of 0x0 in the NXTPTR field terminates the list.
15 - 3
April 5, 2013
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