Table 15.6 Switch Configuration And Status - Renesas IDT 89HPES48H12G2 User Manual

IDT Register Organization
Notes
PES48H12G2 User Manual
Cfg. Register
Size
Offset Mnemonic
0x0000 DWord SWCTL
0x0004 DWord BCVSTS
0x0008 DWord PCLKMODE
0x008C DWord USSBRDELAY
0x0100 DWord SWPART0CTL
0x0104 DWord SWPART0STS
0x0120 DWord SWPART1CTL
0x0124 DWord SWPART1STS
0x0140 DWord SWPART2CTL
0x0144 DWord SWPART2STS
0x0160 DWord SWPART3CTL
0x0164 DWord SWPART3STS
0x0180 DWord SWPART4CTL
0x0184 DWord SWPART4STS
0x01A0 DWord SWPART5CTL
0x01A4 DWord SWPART5STS
0x01C0 DWord SWPART6CTL
0x01C4 DWord SWPART6STS
0x01E0 DWord SWPART7CTL
0x01E4 DWord SWPART7STS
0x0200 DWord SWPART8CTL
0x0204 DWord SWPART8STS
0x0220 DWord SWPART9CTL
0x0224 DWord SWPART9STS
0x0280 DWord SWPART12CTL
0x0284 DWord SWPART12STS
0x02A0 DWord SWPART13CTL
0x02A4 DWord SWPART13STS
0x0300 DWord SWPORT0CTL
0x0304 DWord SWPORT0STS
0x0320 DWord SWPORT1CTL
0x0324 DWord SWPORT1STS
0x0340 DWord SWPORT2CTL
0x0344 DWord SWPORT2STS
0x0360 DWord SWPORT3CTL
Table 15.6 Switch Configuration and Status (Part 1 of 5)
15 - 13
Register Definition
SWCTL - Switch Control (0x0000) on page 17-1
BCVSTS - Boot Configuration Vector Status (0x0004) on page 17-2
PCLKMODE - Port Clocking Mode (0x0008) on page 17-3
USSBRDELAY - Upstream Secondary Bus Reset Delay on page 17-
4
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPART[13:12, 9:0]CTL - Switch Partition x Control on page 17-4
SWPART[13:12, 9:0]STS - Switch Partition x Status on page 17-5
SWPORT[13:12, 9:0]CTL - Switch Port x Control on page 17-5
SWPORT[13:12, 9:0]STS - Switch Port x Status on page 17-6
SWPORT[13:12, 9:0]CTL - Switch Port x Control on page 17-5
SWPORT[13:12, 9:0]STS - Switch Port x Status on page 17-6
SWPORT[13:12, 9:0]CTL - Switch Port x Control on page 17-5
SWPORT[13:12, 9:0]STS - Switch Port x Status on page 17-6
SWPORT[13:12, 9:0]CTL - Switch Port x Control on page 17-5
April 5, 2013