Renesas 89HPES32NT24AG2 Hardware Design Manual

®
Notes
Introduction
compliant System Interconnect switch device family. Information provided in this document is applicable to
the
89HPES24NT6AG2, 89HPES22NT16G2, 89HPES16NT16G2, 89HPES16NT2G2 and 89HPES12NT12G2.
In this document, the PES32NT24AG2 is used as the primary reference. The letters "G2" within the device
names indicate that these devices are capable of GEN2 (5.0 GT/S) serial data speeds. The
PES32NT24AG2 device offers 32 PCIe lanes divided into 24 ports. The PES24NT24G2 device offers 24
PCIe lanes divided into 24 ports, and so on.
recommendations:
PCI Express Interface
Port Configuration
from 0 through 7 and the remaining 16 ports are statically allocated 1 lane with ports labeled from 8 through
23. In a default configuration, SWMODE[3:0] = 0x0, Port 0 is always the upstream port while the remaining
ports are always downstream ports. In a Multi-partition configuration, SWMODE[3:0] = 0xC, or a Multi-parti-
tion with Serial EEPROM initialization configuration, SWMODE[3:0] = 0xD, all ports come up as unattached.
Through a Serial EEPROM or Slave SMBus interface, ports can be configured as an upstream port,
upstream port with NT function, upstream port with NT and DMA functions, NT function, NT with DMA func-
tions, or as downstream ports. All ports can operate at a maximum link width of x2 (i.e. 2 lanes) or x1 (i.e. 1
lane) and support both 2.5 GT/S (Gen1) and 5.0 GT/S (Gen2) speeds.
PES32NT24AG2, PCI device numbering follows the port numbering. Port 0 corresponds to Device 0 on the
upstream bus. Port 1 corresponds to Device 1 on the PES32NT24AG2 virtual PCI bus, Port 2 to Device 2,
and so on.
IDT PCI Express®
24-Port 32-Lane Gen 2 Switch
Hardware Design Guide
This application note provides system design guidelines for IDT's PCI Express® 2.0 base specification
following devices: 89HPES32NT24A[B]G2,
This document also describes the following device interfaces and provides relevant board design
1) PCI Express Interface
2) Reference Clock (REFCLK) Circuitry
3) Reset (Fundamental Reset) Schemes
4) SMBus Interfaces
5) GPIO and JTAG pins
6) Power and Decoupling Scheme
7) Switch Partitioning
Eight of the twenty four ports of the PES32NT24AG2 are statically allocated 2 lanes with ports labeled
Per the PCIe® specification, each switch port is viewed as a virtual PCI-PCI bridge device. In the
Note: Unused PCIe TX and RX lanes are not required to have a termination and can be left
open.
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By Bryan Le
89HPES32NT8A[B]G2,
Application Note
AN-727
89HPES24NT24[A]G2,
May 5, 2011