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Notes
PES48H12G2 User Manual
®
Introduction
This user manual includes hardware and software information on the 89HPES48H12G2, a member of
IDT's PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, "PES48H12G2 Device Overview," provides a complete introduction to the performance
capabilities of the 89HPES48H12G2. Included in this chapter is a summary of features for the device as
well as a system block diagram and pin description.
Chapter 2, "Architectural Overview," provides a high level architectural overview of the PES48H12G2
device.
Chapter 3, "Switch Core," provides a description of the PES48H12G2 switch core.
Chapter 4, "Clocking," provides a description of the PES48H12G2 clocking architecture.
Chapter 5, "Reset and Initialization," describes the PES48H12G2 reset operations and initialization
procedure.
Chapter 6, "Switch Partitions," describes how the PES48H12G2 supports up to 12 active switch parti-
tions.
Chapter 7, "Link Operation," describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 8, "SerDes," describes basic functionality and controllability associated with the Serialiazer-
Deserializer (SerDes) block in PES48H12G2 ports.
Chapter 9, "Theory of Operation," describes the general operational behavior of the PES48H12G2.
Chapter 10, "Hot-Plug and Hot-Swap," describes the behavior of the hot-plug and hot-swap features
in the PES48H12G2.
Chapter 11, "Power Management," describes the power management capability structure located in
the configuration space of each PCI-to-PCI bridge in the PES48H12G2.
Chapter 12, "General Purpose I/O," describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 13, "SMBus Interfaces," describes the operation of the 2 SMBus interfaces on the
PES48H12G2.
Chapter 14, "Multicast," describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.
Chapter 15, "Register Organization," describes the organization of all the software visible registers in
the PES48H12G2 and provides the address space for those registers.
Chapter 16, "PCI to PCI Bridge and Proprietary Port Specific Registers," lists the Type 1 configura-
tion header registers in the PES48H12G2 and provides a description of each bit in those registers.
About This Manual
1
April 5, 2013
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