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Renesas IDT 89HPES12N3A User Manual

Renesas IDT 89HPES12N3A User Manual

Pci express switch
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®
IDT
89HPES12N3A
™
PCI Express® Switch
User Manual
April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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Summary of Contents for Renesas IDT 89HPES12N3A

  • Page 1 ® 89HPES12N3A ™ PCI Express® Switch User Manual April 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES12N3A, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

  • Page 4: Numeric Representations

    Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

  • Page 5: Register Terminology

    Notes The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2. bit 31 bit 0 Address of Bytes within Words: Big Endian...

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Peer-to-Peer Transactions......................3-8 Bus Locking ............................ 3-8 Port Interrupts ..........................3-10 Legacy Interrupt Emulation......................3-10 Standard PCIe Error Detection and Handling................3-11 Physical Layer Errors ......................3-11 Data Link Layer Errors......................3-11 Transaction Layer Errors ...................... 3-12 Routing Errors ........................
  • Page 9 IDT Table of Contents Hot-Plug and Hot-Swap Notes Introduction ............................. 8-1 Hot-Plug I/O Expander ......................8-4 Hot-Plug Interrupts and Wake-up ................... 8-4 Legacy System Hot-Plug Support ..................8-4 Hot-Swap ............................8-6 Configuration Registers Introduction ............................. 9-1 Upstream Port (Port 0) ......................9-3 Downstream Ports (Ports 2 and 4) ..................
  • Page 10 IDT Table of Contents Notes PES12N3A User Manual April 10, 2008...
  • Page 11 List of Tables ® Table 1.1 PES12N3A Device ID ......................1-5 Notes Table 1.2 PES12N3A Revision ID .......................1-5 Table 1.3 PCI Express Interface Pins....................1-6 Table 1.4 SMBus Interface Pins ......................1-6 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins......................... 1-7 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes PES12N3A User Manual April 10, 2008...
  • Page 13 List of Figures ® Figure 1.1 PES12N3A Architectural Block Diagram ................1-3 Notes Figure 1.2 I/O Expansion Application ....................1-3 Figure 1.3 PES12N3A Logic Diagram ....................1-4 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
  • Page 14 IDT List of Figures Notes PES12N3A User Manual viii April 10, 2008...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-41 AERCTL - AER Control (0x118) ......................9-42 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCICMD - PCI Command Register (0x004)....................9-12 PCIECAP - PCI Express Capability (0x040) ...................9-21 PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-22 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-32 PCIEDCTL - PCI Express Device Control (0x048)..................9-23 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-32 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-24 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................9-32...
  • Page 17 IDT Register List Notes SWSTS - Switch Status (0x400) ......................9-50 SWTOCNT - Switch Time-Out Count (0x75C) ..................9-64 SWTOCTL - Switch Time-Out Control (0x750) ..................9-62 SWTORCTL - Switch Time-Out Reporting Control (0x758) ..............9-63 SWTOSTS - Switch Time-Out Status (0x754) ..................9-62 SWTOTSCTL - Switch Time-Out Time-Stamp Control (0x760) ..............9-64 SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) .............9-61 UARBCTC - U-Bus Arbiter Current Transfer Count (0x45C) ..............9-60 UARBTC - U-Bus Arbiter Transfer Count (0x458)...................9-59...
  • Page 18 IDT Register List Notes PES12N3A User Manual April 10, 2008...

  • Page 19: Pes12N3A Device Overview

    Chapter 1 PES12N3A Device Overview ® Introduction Notes The 89HPES12N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and communications/ networking.
  • Page 20 IDT PES12N3A Device Overview Notes Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O –...

  • Page 21: System Diagrams

    IDT PES12N3A Device Overview System Diagrams 3-Port Switch Core Port Scheduler Scheduler Route Table Frame Buffer Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer Logical Logical Logical Logical Logical Logical Logical Logical...

  • Page 22: Logic Diagram

    IDT PES12N3A Device Overview Logic Diagram PEREFCLKP Reference PEREFCLKN Clocks REFCLKM PE0RP[0] PE0TP[0] PE0RN[0] PE0TN[0] PCI Express PCI Express Switch PE0TP[1] PE0RP[1] Switch SerDes Input PE0RN[1] PE0TN[1] SerDes Output Port 0 Port 0 PE0RP[3] PE0TP[3] PE0RN[3] PE0TN[3] PE2RP[0] PE2TP[0] PE2RN[0] PE2TN[0] PCI Express PCI Express...

  • Page 23: System Identification

    IDT PES12N3A Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES12N3A device ID is shown in Table 1.1. PCIe Device Device ID 0x8018 Table 1.1 PES12N3A Device ID...

  • Page 24: Pin Description

    IDT PES12N3A Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES12N3A. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 25: Table 1.5 General Purpose I/O Pins

    IDT PES12N3A Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] General Purpose I/O.

  • Page 26: Table 1.7 Test Pins

    IDT PES12N3A Device Overview Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside the PES12N3A and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 27 IDT PES12N3A Device Overview Notes Signal Type Name/Description PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 1.8 Power and Ground Pins PES12N3A User Manual 1 - 9 April 10, 2008...

  • Page 28: Pin Characteristics

    IDT PES12N3A Device Overview Pin Characteristics Notes Note: Some input pads of the PES12N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
  • Page 29 IDT PES12N3A Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO Low Drive JTAG_TMS pull-up JTAG_TRST_N pull-up External pull-down Table 1.9 Pin Characteristics (Part 2 of 2) Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. Schmitt Trigger Input (STI).
  • Page 30 IDT PES12N3A Device Overview Notes PES12N3A User Manual 1 - 12 April 10, 2008...

  • Page 31: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES12N3A has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.

  • Page 32: Figure 2.2 Non-Common Clock On Upstream; Common Clock On Downstream (Must Disable Spread Spectrum Clock)

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES12N3A Port B Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock) PES12N3A Port B Port A...

  • Page 33: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES12N3A Port B Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Clock Generator Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES12N3A during a fundamental reset when PERSTN is negated.

  • Page 34: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes PERSTN Fundamental Reset. Assertion of this signal resets all logic inside PES12N3A and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES12N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 35 IDT Clocking, Reset, and Initialization Clock Operation Notes The following reset sequence is executed. 1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN). 2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental reset is the result of a one being written to the FRST bit in the SWCTL register).

  • Page 36: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes The PES12N3A provides a reset output signal for each downstream port implemented as a GPIO alter- nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated.

  • Page 37: Upstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes 6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES12N3A registers are updated.

  • Page 38: Downstream Port Reset Outputs

    IDT Clocking, Reset, and Initialization Clock Operation Notes When a downstream secondary bus reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted All TLPs received from corresponding downstream port and queued in the PES12N3A are discarded.

  • Page 39: Power Good Controlled Reset Output

    IDT Clocking, Reset, and Initialization Clock Operation Notes While slot power is enabled, the corresponding downstream port reset output is negated. When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled.
  • Page 40 IDT Clocking, Reset, and Initialization Clock Operation Notes PES12N3A User Manual 2 - 10 April 10, 2008...

  • Page 41: Theory Of Operation

    Chapter 3 Theory of Operation ® Introduction Notes An architectural block diagram of the PES12N3A is shown in Figure 1.1 in Chapter 1. The PES12N3A contains three ports labeled port 0, port 2, and port 4. Port 0 is always the upstream port and ports two and four are always downstream ports.

  • Page 42: Data Paths

    IDT Theory of Operation Notes Buffer Size and Limitations Output and Replay Buffer 4 KB of data or up to 32 TLPs Table 3.2 PES12N3A Buffer Sizes The size of the bus decoupler queue and insertion buffer is shown in Table 3.3. Buffer Size and Limitations Bus Decoupler Queue...

  • Page 43: Switch Core

    IDT Theory of Operation Notes The best case latency for transactions that can be cut-through is shown in Table 3.4. Ingress to Egress Latency (ns) x4 to x4 x4 to x1 x1 to x1 Table 3.4 Latency If the ingress link width is less than the egress link width, then an entire TLP must be received before it can be transmitted on the switch egress port.

  • Page 44: Transaction Routing

    IDT Theory of Operation Transaction Routing Notes The PES12N3A supports routing of all transaction types defined in the PCIe base 1.1 specification. This includes routing of specification-defined transactions as well as those that may be used in vendor defined messages and in future revisions of the PCIe specification. Note: The PES12N3A supports routing of trusted configuration transactions.

  • Page 45: Scheduling And Port Arbitration

    IDT Theory of Operation Notes The generation of “valid” signals is based on PCIe ordering rules and is summarized Table 3.6. The notation x > y indicates that the TLP of type x is older (i.e., has an older time-stamp) than the TLP of type y. It is impossible for two TLPs to have the same timestamp.
  • Page 46 IDT Theory of Operation Notes The candidate vector produced by each port’s ESP is presented to the U-Bus and D-Bus arbiters. – For downstream ports: • The upstream portion of the candidate vector is provided to the D-Bus arbiter. • The downstream portion of the candidate vector is provided to the U-Bus arbiter. An assertion in this portion of the candidate vector indicates a peer-to-peer or downstream route-to-self transfer.

  • Page 47: Figure 3.2 U-Bus Arbitration

    IDT Theory of Operation Notes For downstream-to-upstream transfers, the upstream port’s port arbiter selects the transaction that is initiated. The upstream port arbiter implements both a hardwired fixed round robin algorithm as well as a weighted round robin with 32 phases algorithm as defined by the PCIe base 1.1 specification. The arbitra- tion algorithm, as well as weighted round robin arbitration parameters, are software selectable.

  • Page 48: Peer-To-Peer Transactions

    IDT Theory of Operation Notes pler queue transfer is initiated). However, since the upstream input frame buffer has a queue per transac- tion type, it is possible for multiple upstream to downstream transactions to simultaneously request service. In such a situation, the oldest transaction (i.e., the one with the oldest time-stamp) is selected. Peer-to-Peer Transactions The broadest definition of a peer-to-peer transaction is a transaction that originates at one endpoint and targets another endpoint (i.e., the endpoints are peers).
  • Page 49 IDT Theory of Operation Notes stream port. Regardless of the success of a lock, the root complex is required to terminate all lock sequences with an Unlock message. The upstream port lock associated with an unsuccessful completion is released when this Unlock message is received. The CplDLk transaction obeys PCI ordering rules, meaning that all queued posted requests at the locked downstream port destined to the upstream port are completed prior to the CplDLk being transmitted.

  • Page 50: Port Interrupts

    IDT Theory of Operation Port Interrupts Notes The upstream port, port 0, does not generate legacy interrupts or MSIs. Downstream ports support generation of legacy interrupts and MSIs. The following are sources of downstream port interrupts and MSIs. – Downstream port’s hot-plug controller –...

  • Page 51: Standard Pcie Error Detection And Handling

    IDT Theory of Operation Notes An Assert_INTx message is sent to the root by the upstream port (i.e., port 0), when the aggregated state of the corresponding interrupt in the upstream port transitions from a negated to an asserted state. A Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre- sponding interrupt in the upstream port transitions from an asserted to a negated state.

  • Page 52: Transaction Layer Errors

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section TLP ending in ENDB with LCRC that does not 3.5.3.1 TLP discarded match inverted calculated LCRC TLP received with incorrect LCRC 3.5.3.1 Correctable error processing TLP received with sequence number not equal 3.5.3.1 Correctable error processing to NEXT_RCV_SEQ and this is not a duplicate...

  • Page 53: Table 1.1 Table

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section Completer abort 2.3.1 Not applicable. The PES12N3A Completion time-out never generates non-posted transactions as a requester. Unexpected completion 2.3.2 For the non-advisory cases: non- fatal error processing. Advisory cases: correctable error processing.

  • Page 54: Routing Errors

    IDT Theory of Operation Notes TLP Type Error Check I/O read or write request LENGTH = 1 (doubleword) TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000 Configuration read or write request LENGTH = 1 (doubleword) TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000 Message Requests...

  • Page 55: Switch Specific Error Detection And Handling

    IDT Theory of Operation Notes Address Routed TLPs – TLPs whose address decoding indicates they are to route back to the port on which they were received. – TLPs received on the upstream port that match the upstream port’s address range but which do not match a downstream port’s address range (i.e., TLPs that do not route through the PES12N3A).

  • Page 56: Switch Time-Outs

    IDT Theory of Operation Switch Time-Outs Notes The switch core discards any TLP that reaches the head of an IFB queue and is more than 64 seconds old. This includes posted, non-posted, completion and inserted TLPs. Although this feature is enabled by default, it may be disabled by setting the Enable Switch Time-outs (ETO) bit in a port’s Switch Time-Out Control (SWTOCTL) register.

  • Page 57: Tlp Processing

    IDT Theory of Operation Notes If a parity error is detected by the DL layer of an egress port, then the TLP is nullified by inverting the computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are discarded.
  • Page 58 IDT Theory of Operation Notes requests that are Message Signaled Interrupts (MSIs), and Message requests (except where specifically permitted). Since MSIs cannot be distinguished from memory write transactions by the switch, the no-snoop attribute of MSIs will be modified. PES12N3A User Manual 3 - 18 April 10, 2008...

  • Page 59: Link Operation

    Chapter 4 Link Operation ® Introduction Notes The PES12N3A contains three x4 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES12N3A supports automatic polarity inversion as required by the PCIe specification. Polarity inversion is a function of the receiver and not the transmitter.

  • Page 60: Link Retraining

    IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES12N3A PES12N3A PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal PExRP[0] lane 0 PExRP[0]...

  • Page 61: Link Down

    IDT Link Operation Link Down Notes When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR).

  • Page 62: Active State Power Management

    IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.3 PES12N3A ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is independent of power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.

  • Page 63: Link Status

    IDT Link Operation Link Status Notes Associated with each port is a Port Link Up (PxLINKUP) status output and a Port Activity (PxACTIVE) status output. These outputs are provided on I/O Expander 4. See section I/O Expanders on page 6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
  • Page 64 IDT Link Operation Notes PES12N3A User Manual 4 - 6 April 10, 2008...

  • Page 65: General Purpose I/O

    Chapter 5 General Purpose I/O ® Introduction Notes The PES12N3A has 8 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 66: Gpio Pin Configured As An Input

    IDT General Purpose I/O GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.

  • Page 67: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES12N3A contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES12N3A, allowing every register in the device to be read or written by an external SMBus master.

  • Page 68: Master Smbus Interface

    IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses. Thus, multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.

  • Page 69: Table 6.2 Pes12N3A Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.2 PES12N3A Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.

  • Page 70: Figure 6.3 Sequential Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.3 Sequential Double Word Initialization Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end...

  • Page 71: Table 6.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence . The correct result should always be 0xFF (i.e., all ones). Checksum checking may be disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the SMBus Control (SMBUSCTL) register.

  • Page 72: I/O Expanders

    IDT SMBus Interfaces Notes Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results. SMBus errors may occur when accessing the serial EEPROM. If an error occurs, it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access.
  • Page 73 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES12N3A to I/O expander zero: – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through I/O-0.7) to I/O expander register 2. –...
  • Page 74 IDT SMBus Interfaces Notes expander, the PES12N3A will not issue a master SMBus transaction to read the updated state of the I/O expander inputs more frequently than once every 40 milliseconds (i.e., the I/O expander update period). This delay in sampling may be used to eliminate external debounce circuitry. The I/O expander interrupt request output is negated whenever the input values are read or when the input pin changes state back to the value previously read.

  • Page 75: Table 6.5 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes I/O Expander 0 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P2APN Port 2 attention push button input 1 (I/O-0.1) P2PDN Port 2 presence detect input 2 (I/O-0.2) P2PFN Port 2 power fault input 3 (I/O-0.3) P2MRLN Port 2 manually-operated retention latch (MRL) input...

  • Page 76: Slave Smbus Interface

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 9 (I/O-1.1) Reserved Tie high 10 (I/O-1.2) P2PWRGDN Port 2 power good input 11 (I/O-1.3) Reserved Tie high 12 (I/O-1.4) P4PWRGDN Port 4 power good input 13 (I/O-1.5) Reserved Tie high or low 14 (I/O-1.6) Reserved Tie high or low...

  • Page 77: Initialization

    IDT SMBus Interfaces Initialization Notes Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-4). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The address is specified by the SSMBADDR[5,3:1] signals as shown in Table 6.8. Address Bit Address Bit Value SSMBADDR[1]...

  • Page 78: Table 6.9 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Notes Name Description End of transaction indicator. Setting both START and END signifies a single transaction sequence. 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence. START Start of transaction indicator.

  • Page 79: Table 6.10 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Name Description Position CCODE Command Code. Slave Command Code field described in Table 6.9. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field. The byte count field indi- cates the number of bytes following the byte count field when performing a write or setting up for a read.

  • Page 80: Table 6.12 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Bit Field Name Type Description Read/Write CSR Operation. This field encodes the CSR operation to be performed. 0 - CSR write 1 - CSR read Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus and Clear transaction was not claimed by a device.

  • Page 81: Table 6.13 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes OTHERERR LAERR NAERR Figure 6.7 Serial EEPROM Read or Write CMD Field Format Bit Field Name Type Description Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address.

  • Page 82: Figure 6.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec

    IDT SMBus Interfaces Notes PES12N3A Slave CCODE BYTCNT=3 CMD=read ADDRL ADDRU SMBus Address START,END PES12N3A Slave CCODE (PES12N3A not ready with data) SMBus Address START,END PES12N3A Slave CCODE PES12N3A Slave BYTCNT=7 CMD (status) ADDRL SMBus Address START,END SMBus Address ADDRU DATALL DATALM DATAUM...

  • Page 83: Figure 6.11 Serial Eeprom Write Using Smbus Block Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES12N3A Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES12N3A Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled PES12N3A User Manual...

  • Page 84: Figure 6.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES12N3A Slave CCODE CMD=read ADDRL SMBus Address START, Word PES12N3A Slave CCODE ADDRU SMBus Address END, Byte PES12N3A Slave CCODE (PES12N3A not ready with data) SMBus Address START,Word PES12N3A Slave CCODE SMBus Address START,Word PES12N3A Slave CMD (status) ADDRL SMBus Address...

  • Page 85: Power Management

    Chapter 7 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES12N3A is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 86: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the state.

  • Page 87: Power Budgeting Capability

    IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES12N3A receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES12N3A transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 88 IDT Power Management Notes PES12N3A User Manual 7 - 4 April 10, 2008...

  • Page 89: Notes

    Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES12N3A in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 90: Figure 8.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES12N3A Port 2 Port 4 PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES12N3A Master SMBus Port 2 Port 4 SMBus I/O...

  • Page 91: Table 8.1 Downstream Port Hot-Plug Signals

    IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES12N3A in an application involving an add-in card hot-plugged into a downstream slot. Associated with each downstream port in the PES12N3A is a hot- plug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capa- bilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).

  • Page 92: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes The default value of hot-plug registers following a hot or fundamental reset may be configured via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result of serial EEPROM initialization.

  • Page 93: Figure 8.4 Pes12N3A Hot-Plug Event Signalling

    IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.

  • Page 94: Hot-Swap

    IDT Hot-Plug and Hot-Swap Hot-Swap Notes The PES12N3A is hot-swap capable and meets the following requirements: – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.). – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

  • Page 95: Configuration Registers

    Chapter 9 Configuration Registers ® Introduction Notes Each software-visible register in the PES12N3A is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES12N3A that cannot be accessed by the root. Each software- visible register in the PES12N3A has a system address.

  • Page 96: Figure 9.1 Port Configuration Space Organization

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting Enhanced Capability Switch Control 0x400...

  • Page 97: Upstream Port (Port 0)

    IDT Configuration Registers Upstream Port (Port 0) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 98 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 99 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-42 0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 9-42 0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page...
  • Page 100 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword P0_PWRBDV3 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x310 Dword P0_PWRBDV4 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x314 Dword P0_PWRBDV5 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on...
  • Page 101 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page 9-62 0x74C Dword P0_SWPECNT SWPECNT - Switch Parity Error Count (0x74C) on page 9-62 0x750 Dword P0_SWTOCTL SWTOCTL - Switch Time-Out Control (0x750) on page 9-62 0x754...

  • Page 102: Downstream Ports (Ports 2 And 4)

    IDT Configuration Registers Downstream Ports (Ports 2 and 4) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 103 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 104 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F0 Dword Px_SSIDSSVIDCA SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) on page 9-36 0x0F4 Dword Px_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on page 9-36 0x0F8 Word Px_ECFGADDR...
  • Page 105 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-50 0x28C Dword Px_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on page 9-50 0x300 Dword Px_PWRBDV0 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x304...

  • Page 106: Register Definitions

    IDT Configuration Registers Register Definitions Notes Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-5. DID - Device Identification Register (0x002) Field Default...
  • Page 107 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADSTEP Address Data Stepping. Not applicable. SERRE SERR Enable. Non-fatal and fatal errors detected by the bridge are reported to the Root Complex when this bit is set or the bits in the PCI Express Device Control register are set (see PCIEDCTL - PCI Express Device Control (0x048) on page 9-23).
  • Page 108 IDT Configuration Registers Notes Field Default Type Description Field Name Value RTAS Received Target Abort. Not applicable. RMAS Received Master Abort. Not applicable. RW1C Signalled System Error. This bit is set when the bridge sends a ERR_FATAL or ERR_NONFATAL message and the SERR Enable (SERRE) bit is set in the PCICMD regis- ter.
  • Page 109 IDT Configuration Registers Notes HDR - Header Type Register (0x00E) Field Default Type Description Field Name Value 0x01 Header Type. This value indicates a type 1 header with a single function bridge layout. BIST - Built-in Self Test Register (0x00F) Field Default Type...
  • Page 110 IDT Configuration Registers Notes SUBUSN - Subordinate Bus Number Register (0x01A) Field Default Type Description Field Name Value SUBUSN Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
  • Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error. This bit is controlled by the Parity Error Response Enable bit in the Bridge Control register. If the Parity Response Enable bit is cleared, then this bit is never set.
  • Page 112 IDT Configuration Registers Notes PMBASE - Prefetchable Memory Base Register (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 -(prefmem32) 32-bit prefetchable memory addressing. 0x1 - (prefmem64) 64-bit prefetchable memory addressing. Reserved Reserved field.
  • Page 113 IDT Configuration Registers Notes IOBASEU - I/O Base Upper Register (0x030) Field Default Type Description Field Name Value 15:0 IOBASEU 0xFFFF I/O Address Base Upper. This field specifies the upper 16- bits of IOBASE. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 114 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot-plug by the downstream ports. This field should only be configured with values of 0x0 through 0x4.

  • Page 115: Pci Express Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
  • Page 116 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. The default value corresponds to 2048 bytes. Phantom Functions Supported.
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:26 CSPLS Captured Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for the upstream port.
  • Page 118 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:12 MRRS Maximum Read Request Size. The bridge does not gener- ate transactions larger than 128 bytes and passes transac- tions through the bridge with the size unmodified. Therefore, this field has no functional effect on the behavior of the bridge.
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum WDTH link width of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
  • Page 120 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 PORTNUM Port 0: 0x0 Port Number. This field indicates the PCI express port num- Port 2: 0x2 ber for the corresponding link. Port 4: 0x4 PCIELCTL - PCI Express Link Control (0x050) Field Default Type...
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value LBWINTEN Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the LBWSTS bit has been set in the PCIELSTS register. If the LBN field in the PCIELCAP register is cleared, this field is hardwired to zero.
  • Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value LBWSTS RW1C Link Bandwidth Management Status. This bit is set to indicate that either of the following have occurred without the link transitioning through the DL_Down state. A link retraining initiated by setting the LRET bit in the PCIELCTL register has completed.
  • Page 123 IDT Configuration Registers Notes Field Default Type Description Field Name Value Hot-Plug Capable. This bit is set if the slot corresponding to the port is capable of supporting hot-plug operations. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 124 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSCE MRL Sensor Change Enable. This bit when set enables the generation of a Hot-Plug interrupt or wake-up event on a MRL sensor change event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
  • Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.
  • Page 126 IDT Configuration Registers Notes PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value 31:0 Reserved Reserved field. PCIEDCTL2 - PCI Express Device Control 2 (0x068) Field Default Type Description Field Name Value 15:0 Reserved Reserved field.

  • Page 127: Power Management Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:6 Reserved Reserved field. PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) Field Default Type...
  • Page 128 IDT Configuration Registers Notes Field Default Type Description Field Name Value DEVSP Device Specific Initialization. The value of zero indicates that no device specific initialization is required. 24:22 AUXI AUX Current. not used D1 Support. This field indicates that the PES12N3A does not support D1.

  • Page 129: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value BPCCE Bus Power/Clock Control Enable. Does not apply to PCI Express. 31:24 DATA Data. This optional field is not implemented. Message Signaled Interrupt Capability Structure MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) Field Default Type...

  • Page 130: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) Field Default Type Description Field Name Value 31:0 UADDR Upper Message Address. This field specifies the upper portion of the DWORD address of the MSI memory write transaction. If the contents of this field are non-zero, then 64-bit address is used in the MSI memory write transaction.

  • Page 131: Extended Configuration Space Access Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:16 SSID Subsystem ID. This field identifies the add-in card or sub- system. SSID values are assigned by the vendor. Extended Configuration Space Access Registers ECFGADDR - Extended Configuration Space Access Address (0x0F8) Field Default Type...
  • Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:20 NXTPTR 0x200 Next Pointer. AERUES - AER Uncorrectable Error Status (0x104) Field Default Type Description Field Name Value UDEF RW1C Undefined. This bit is no longer used in this version of the Sticky specification.
  • Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value DLPERR Data Link Protocol Error Mask. When this bit is set, the Sticky corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 134 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specification. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported...
  • Page 135 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in Sticky the AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit Sticky in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.

  • Page 137: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 3rd doubleword of the Sticky TLP header that resulted in the first reported uncorrectable error.

  • Page 138: Pci Express Virtual Channel Capability

    IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capability structure. 19:16 CAPVER Capability Version.
  • Page 139 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. This field contains the offset of the VC arbitration table from the base address of the Vir- tual Channel Capability structure in double quad words (16 bytes).
  • Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value Advanced Packet Switching. Not supported. RJST Reject Snoop Transactions. No supported for switch ports. 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field.
  • Page 141 IDT Configuration Registers Notes VCR0STS - VC Resource 0 Status (0x218) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PATS Port Arbitration Table Status. This bit indicates the coher- ency status of the port arbitration table associated with the VC resource and is valid only when the port arbitration table is used by the selected arbitration algorithm.
  • Page 142 IDT Configuration Registers Notes VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224) Field Default Type Description Field Name Value PHASE8 Phase 8. This field contains the port ID for the correspond- ing port arbitration period. PHASE9 Phase 9. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 143: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 11:8 PHASE26 Phase 26. This field contains the port ID for the correspond- ing port arbitration period. 15:12 PHASE27 Phase 27. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 144: Switch Control And Status Registers

    IDT Configuration Registers Notes PWRBD - Power Budgeting Data (0x288) Field Default Type Description Field Name Value 31:0 DATA Data. If the Data Value Select (DVSEL) field in the Power Budgeting Data Select register contains a value of zero through 31, then this field returns the contents of the corre- sponding Power Budgeting Data Value (PWRBDVx) regis- ter.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value MSMB- HWINIT Master SMBus Slow Mode. This bit reflects the value of the SMODE MSMBSMODE signal sampled during the fundamental reset. REFCLKM HWINIT PCI Express Reference Clock Mode Select. This bit reflects the value of the REFCLKM signal sampled during the fundamental reset.
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except Sticky the SMBus interface remains in a reset state. In this state, registers in the device may be initialized by the slave SMBus interface.
  • Page 147 IDT Configuration Registers Notes HPCFGCTL - Hot-Plug Configuration Control (0x408) Field Default Type Description Field Name Value IPXAPN Invert Polarity of PxAPN. When this bit is set, the polarity Sticky of the PxAPN input is inverted in all ports. IPXPDN Invert Polarity of PxPDN.
  • Page 148 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 RST2PWR 0x14 Reset Negation. This field contains the delay from negation Sticky of a downstream port’s reset to disabling of a downstream port’s power in units of 10 mS. A value of zero corresponds to no delay.
  • Page 149 IDT Configuration Registers Notes SMBUSSTS - SMBus Status (0x424) Field Default Type Description Field Name Value Reserved Reserved field. SSMBADDR HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface. Reserved Reserved field. 15:9 MSMBADDR HWINIT Master SMBus Address.
  • Page 150 IDT Configuration Registers Notes Field Default Type Description Field Name Value MSMBIOM Master SMBus Ignore Other Masters. When this bit is set, Sticky the master SMBus proceeds with transactions regardless of whether it won or lost arbitration. ICHECKSUM Ignore Checksum Errors. When this bit is set, serial Sticky EEPROM initialization checksum errors are ignored (i.e., the checksum always passes).
  • Page 151 IDT Configuration Registers Notes Field Default Type Description Field Name Value BUSY EEPROM Busy. This bit is set when a serial EEPROM read or write operation is in progress. 0x0 -(idle) serial EEPROM interface idle 0x1 -(busy) serial EEPROM interface operation in progress DONE RW1C EEPROM Operation Completed.
  • Page 152 IDT Configuration Registers Notes Field Default Type Description Field Name Value DONE RW1C I/O Expander Operation Done. This bit is set when any of the following conditions occurs: - RELOADIOEX bit in this register is written, the corre- sponding I/O expander is selected by the SELECT field in this register, and the corresponding IO expander SMBus transaction completes.
  • Page 153 IDT Configuration Registers Notes Field Default Type Description Field Name Value P2GPEE Port 2 General Purpose Event Enable. When this bit is Sticky set, the hot-plug INTx, MSI and PME event notification mechanisms defined by the PCIe base 1.1 specification are disabled for port 2 and are instead signalled through Gen- eral Purpose Event (GPEN) signal assertions.
  • Page 154 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 U2STC 0x01 Upstream to Self Transfer Count. This field contains the Sticky upstream to self transfer count. The U2SCTC field in the UARBCTC register is set to this value after each arbitration period.

  • Page 155: Internal Switch Error Control And Status Registers

    IDT Configuration Registers Notes SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) Field Default Type Description Field Name Value 31:0 PRESETVAL Time-Stamp Preset Value. A write to this register will cause bits 34 through three of the time-stamp counter associated with all ports to take on the value written and bits two through zero to be set to zero.
  • Page 156 IDT Configuration Registers Notes SWPERCTL - Switch Parity Error Reporting Control (0x748) Field Default Type Description Field Name Value EEPE End-to-End Parity Error Reporting. This field controls the manner in which end-to-end parity errors detected at this port are reported. An end-to-end parity error is reported as specified in this field whenever the EEPE bit in the Switch Parity Error Status (SWPESTS) register transitions from a zero to a one.
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value CPTLPTO RW1C Completion TLP Time-Out. This bit is set when a TLP is discarded from the port’s IFB completion queue because of a time-out. ITLPTO RW1C Inserted TLP Time-Out. This bit is set when a TLP is dis- carded from the port’s IFB insertion queue because of a time-out.
  • Page 158 IDT Configuration Registers Notes Field Default Type Description Field Name Value ITLPTO Inserted TLP Time-Out Reporting. This field controls the Sticky manner in which inserted TLP time-outs are reported. A time-out is reported as specified in this field whenever the corresponding bit in the Switch Time-Out Status (SWTOSTS) register transitions from a zero to a one.
  • Page 159 IDT Configuration Registers Notes Field Default Type Description Field Name Value 30:22 TCOUNT 0x1DD Terminal Count. This field contains the value associated Sticky with bits 24 to 32 which signify a terminal count. When the time-stamp counter is greater than or equal to this value, then time-stamp epoch values contained in bits 33 and 34 of the time-stamp are incremented.The default value of 0x1DD corresponds to an epoch interval of ~32 S.
  • Page 160 IDT Configuration Registers Notes PES12N3A User Manual 9 - 66 April 10, 2008...

  • Page 161: Jtag Boundary Scan

    Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES12N3A: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 162: Table 10.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.

  • Page 163: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PE0RN[3:0] face PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0] PE5TP[3:0] PE6RN[3:0]...

  • Page 164: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PCI Express Inter- PEREFCLKN[2:1] — face (cont.) PEREFCLKP[2:1] — REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O GPIO[7:0] System Pins CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] —...

  • Page 165: Figure 10.3 Diagram Of Observe-Only Input Cell

    IDT JTAG Boundary Scan Notes Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor- rect data to be latched into a cell.

  • Page 166: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes The output enable cells are also output cells. The simplified logic is shown in Figure 10.5. shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 10.5 Diagram of Bidirectional Cell...

  • Page 167: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 168: Clamp

    IDT JTAG Boundary Scan Notes Therefore, instead of having to shift many times to get a value through the PES12N3A, the user only needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
  • Page 169 IDT JTAG Boundary Scan Notes the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test- Logic-Reset controller state by continuously holding JTAG_TRST_N low and/or JTAG_TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it. PES12N3A User Manual 10 - 9 April 10, 2008...
  • Page 170 IDT JTAG Boundary Scan Notes PES12N3A User Manual 10 - 10 April 10, 2008...
  • Page 171 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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