Table 13.4 I/O Expander Default Output Signal Value - Renesas IDT 89HPES48H12G2 User Manual

Pci express switch
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IDT SMBus Interfaces
Notes
PES48H12G2 User Manual
Outputs for ports that are disabled, mapped to GPIO alternate functions, or are not implemented in that
configuration, are set to their negated value (e.g., the power indicator is turned off, the link is down, there is
no activity, etc.). The default value of I/O expander outputs is shown in Table 13.4. Note that this default
value may be modified via serial EEPROM or SMBus configuration prior to SMBus initialization by changing
the state of the PCI Express Slot Control Register (PCIESCTL) or Hot-Plug Configuration Control (HPCF-
GCTL).
Hot-Plug Signal
PxAIN
PxPIN
PxPEP
PxILOCKP

Table 13.4 I/O Expander Default Output Signal Value

The following I/O expander configuration sequence is issued by PES48H12G2 to I/O expanders 0
through 7, 9 and 10 (i.e., the ones that contain general port hot-plug signals and electromechanical interlock
signals).
– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through
I/O-0.7) to I/O expander register 2.
– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 3.
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-
0.0 through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select inputs/outputs in the upper eight I/O expander bits (i.e., I/
O-1.0 through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7)
– read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7)
The following I/O expander configuration sequence is issued by PES48H12G2 to I/O expanders 8 and
11 (i.e., the ones that contain MRL and fundamental reset inputs).
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select all inputs in the lower eight I/O expander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all inputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7)
– read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7)
Description
Attention indicator output (off)
Power indicator output (on)
Power enable output (on)
Electromechanical interlock (negated - off)
13 - 7
Default
Value
1
0
1
0
April 5, 2013

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