Table 11.1 Pes48H12G2 Power Management State Transition Diagram - Renesas IDT 89HPES48H12G2 User Manual

IDT Power Management
Notes
PES48H12G2 User Manual
Partition Reset
Figure 11.1 PES48H12G2 Power Management State Transition Diagram
From State To State
any D0 Uninitialized
D0 Uninitialized D0 Active
D0 Active D3
hot
D3 D0 Uninitialized
hot
D3 D3
hott cold

Table 11.1 PES48H12G2 Power Management State Transition Diagram

PCI-to-PCI bridge Functions have the following behavior when in the D3
– A bridge accepts, processes and completes all type 0 configuration read and write requests.
– Accepts and processes all message requests that target the bridge.
– All requests received by the bridge on the primary interface, except as noted above, are treated
as unsupported requests (UR).
– Any error message resulting from the receipt of a TLP is reported in the same manner as when
the bridge is not in D3
hot
• This requires transitioning the link to the L0 state when error reporting is enabled and the link is
not in L0.
– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no
error message is generated).
– All completions that target the bridge are treated as unexpected completions (UC).
– Completions flowing in either direction through the bridge are routed as normal. This behavior of
the bridge does not differ from that of the bridge when it is in the D0 power management state.
11 - 2
D0
Uninitialized
D0
Active
D3
hot
D3
cold
Description
Partition reset (any type).
Function configured by software
The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to the D3
The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to D0 state.
Power is removed from the device.
(e.g, generation of an ERR_NONFATAL message to the root).
state.
hot
power management state.
hot
April 5, 2013