Table 7.2 Gen1 Compatibility Mode: Bits Cleared In Training Sets - Renesas IDT 89HPES48H12G2 User Manual

IDT Link Operation
Notes
PES48H12G2 User Manual
When a PES48H12G2 port operates in Gen1 Compatibility Mode, the PHY does not set the following
bits in Table 7.2 in the training sets that it transmits.
Training
Symbol
Set
TS1 4
TS2 4

Table 7.2 Gen1 Compatibility Mode: bits cleared in training sets

A PES48H12G2 port exits Gen1 Compatibility Mode by clearing the G1CME field in the PHYLCFG0
register and fully retraining the link (i.e., via the FLRET bit the PHYLSTATE0 register). When this occurs,
the training set bits listed in Table 7.2 behave per the PCI Express 2.0 definition.
PCIe 1.1 and
Bit earlier
Definition
2 Reserved 5.0 GT/s Data Rate Support
6 Multiple meanings (refer to PCI Express
2.0 Specification)
7 Speed Change
2 Reserved 5.0 GT/s Data Rate Support
6 Multiple meanings (refer to PCI Express
2.0 Specification)
7 Speed Change
7 - 17
PCI Express 2.0 Definition
April 5, 2013