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IDT Theory of Operation
Notes
PES48H12G2 User Manual
It follows that MSIs generated by the switch's ports can't fall within the multicast BAR aperture in the
partition. When this occurs, the behavior is undefined.
EN bit in
Unmasked
MSICAP
Interrupt
Register
Asserted
1
0
0
Negated
1
0
0
Downstream Port Interrupts
Downstream ports support generation of legacy interrupts and MSIs. The following are sources of down-
stream port interrupts and MSIs.
– Downstream port's hot-plug controller
– Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the
PCIELSTS register when interrupt notification is enabled for these bits)
When a port is configured to generate INTx messages, only INTA is used.
Legacy Interrupt Emulation
Each PES48H12G2 partition supports legacy PCI INTx emulation. Rather than use sideband INTx
signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An
Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message
is used to signal its negation.
Within each partition, the PES48H12G2 maintains an aggregated INTx state for each of the four inter-
rupt signals (i.e., A through D) at each port. An Assert_INTx message is sent to the root by the upstream
port when the aggregated state of the corresponding interrupt in the upstream port transitions from a
negated to an asserted state. A Deassert_INTx message is sent to the root by the upstream port when the
aggregated state of the corresponding interrupt in the upstream port transitions from an asserted to a
negated state.
PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port. This mapping is summarized in Table 9.3.
INTXD bit
in PCICMD
Register
X
MSI message generated
0
Assert_INTA message request generated to switch
core
1
None
X
None
0
Deassert_INTA message request generated to
switch core
1
None
Table 9.2 Downstream Port Interrupts
9 - 2
Action
April 5, 2013
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