Switch Configuration And Status Registers; Switch Control And Status Registers - Renesas IDT 89HPES48H12G2 User Manual

Switch Control and Status Registers

SWCTL - Switch Control (0x0000)
Bit Field
Field Name
1:0 Reserved
2 RSTHALT
3 REGUNLOCK
4 PWRBDVUL
8:5 Reserved
PES48H12G2 User Manual
Switch Configuration and
®
Default
Type
Value
RO 0x0 Reserved field.
RW HWINIT Reset Halt. When this bit is set, all of the switch logic except the
SWSticky SMBus interface remains in a quasi-reset state. In this state, regis-
ters in the device may be initialized by the slave SMBus interface.
When this bit is cleared, normal operation ensues.
Setting or clearing this bit has no effect outside of the switch funda-
mental reset sequence outlined in section Switch Fundamental
Reset on page 5-3.
The initial value of this bit is that of the RSTHALT signal in the boot
configuration vector.
RW 0x0 Register Unlock. When this bit is set, the contents of registers and
SWSticky fields of type Read and Write when Unlocked (RWL) are modified
when written. When this bit is cleared, all registers and fields
denoted as RWL become read-only.
While the initial value of this field is cleared, it is set during a switch
fundamental reset sequence to allow the serial EEPROM to modify
the contents of RWL fields.
RWL 0x0 Power Budgeting Data Value Unlock. When this bit is set, the
SWSticky Power Budgeting Data Value [7:0] (PWRBDV[7:0]) registers in all
ports may be read and written. When this bit is cleared, then the
PWRBDV registers in all ports are read-only.
RO 0x0 Reserved field.
17 - 1
Status Registers
Description
Chapter 17
April 5, 2013