Link States; Active State Power Management - Renesas IDT 89HPES48H12G2 User Manual

Pci express switch
Table of Contents

Advertisement

IDT Link Operation
Notes
PES48H12G2 User Manual

Link States

PES48H12G2 ports support the following link states:
– L0
Fully operational link state
– L0s
Automatically entered low power state with shortest exit latency
– L1
Lower power state than L0s
May be automatically entered or directed by software by placing the device in the D3
– L2/L3 Ready
The L2/L3 state is entered after the acknowledgement of a PME_Turn_Off Message.
There is no TLP or DLLP communications over a link in this state.
Note that in this state, the link is considered 'up'.
– L3
Link is completely unpowered and off
– Link Down
A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the
LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states.
L0s
Figure 7.6 PES48H12G2 ASPM Link Sate Transitions

Active State Power Management

The operation of link Active State Power Management (ASPM) is orthogonal to device power manage-
ment. Once ASPM is enabled, ASPM link state transitions are initiated by hardware without software
involvement.
The PES48H12G2 ASPM supports the required receiver L0s state as well as the optional transmitter
L0s and L1 states. ASPM is enabled via the ASPM field in the function's link control register (PCIELCTL).
L1
L0
L2/L3 Ready
L3
7 - 11
hot
Fundamental Reset
Hot Reset
Etc.
Link Down
April 5, 2013
state

Advertisement

Table of Contents
loading

Table of Contents