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Notes
PES48H12G2 User Manual
Use of Hypertext
In Chapter 15, Tables 15.4, 15.5 and 15.6 contain register names and page numbers highlighted in blue
under the Register Definition column. In pdf files, users can jump from this source table directly to the regis-
ters by clicking on the register name in the source table. Each register name in the table is linked directly to
the appropriate register in the register section of Chapters 16 and 17. To return to the source table after
having jumped to the register section, click on the same register name (in blue) in the register section.
Reference Documents
[1] PCI Express Base Specification Revision 2.0., December 20, 2006, PCI-SIG.
[2] Multicast Engineering Change Notice to [1]., May 8, 2008, PCI-SIG.
[3] Internal Error Reporting Engineering Change Notice to [1]., April 24, 2008, PCI-SIG.
[4] SMBus Specification, Version 2.0, August 3, 2000, SBS Implementers Forum.
Revision History
October 6, 2008: Initial publication of preliminary user manual.
November 7, 2008: In Chapter 1, Table 1.5, added footnote advising users to connect unused port clock
pins to Vss.
January 12, 2009: On page 3-6, revised Port Arbitration section. On page 6-5, table reference was
changed from 15.5 to 15.4.
January 22, 2009: In Chapter 13, Table 13.16, changed the description for bit USA. In Chapter 16,
PCIEDCTL register, changed the description for bit ERO.
February 9, 2009: In Chapter 1: Table 1.4, for Port 0 Serial Data Receive/Transmit signals, deleted
statement that port 0 is the upstream port; Table 1.8, revised Description for SWMODE[3:0]; Table 1.10,
added "3.3V is preferred" for signal V
Software Management of Link Speed.
February 18, 2009: In Chapter 7, added a note under L2/L3 Ready in Link States section. In Chapter
16, modified Description for REG and EREG fields in the ECFGADDR register, GADDR field in the
GASAADDR register, DATA field in the GASADATA register, and RSE field in the SECSTS register. In
Chapters 15 and 16, added PHYLSTATE0 (0x540) register.
March 18, 2009: In Table 13.12, the address value was changed from zero to 1 for bits 3 and 5.
April 6, 2009: In Chapter 5, revised text in Partition Hot Reset section and added text in several sub-
sections of Switch Mode Dependent Initialization section. Revised Chapter 6, Switch Partitions, including
new sections Partition State Change, and Partition and Port Configuration. Made changes in register fields
in Chapters 16 and 17 (Bridge and Switch Registers), to conform with device specification and validation.
April 21, 2009: In Table 1.8, deleted reference to pull-down value of 251K ohm resistor for all
PxMERGEN pins. In Footnote 1 for Table 1.11, internal resistor pull-down value was changed to 91K ohms.
In Chapter 17, changed "Bit x in this field corresponds to GPIO pin (x+31)" to "Bit x in this field corresponds
to GPIO pin (x+32)" in the GPIOFUNC1, GPIOCFG1, and GPIOD1 registers. Changed title for Table 13.12.
April 27, 2009: ZB silicon was added to Table 1.3.
May 6, 2009: In Chapter 5, under section Switch Fundamental Reset, deleted bullet referencing
SWFRST bit.
May 14, 2009: In Table 1.11, changed CML to HCSL for PCIe reference clocks.
May 28, 2009: In Chapter 7, revised Crosslink section. In Chapter 8, Tables 8.2, 8.3 and 8.4, changed
column title of TX_EQ_MODE to reflect the register field used to control TX equalization depending on the
operating mode of the link (e.g., TX_EQ_3DBG1). In Chapter 13, revised Introduction section and deleted
I/O. In Chapter 7, deleted footnote in 2nd paragraph under section
DD
5
April 5, 2013
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