Renesas IDT 89HPES4T4 Manuals

Manuals and User Guides for Renesas IDT 89HPES4T4. We have 1 Renesas IDT 89HPES4T4 manual available for free PDF download: User Manual

Renesas IDT 89HPES4T4 User Manual (153 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 2.07 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
9
PES4T4 Device Overview
21
Introduction
21
List of Features
21
System Diagrams
22
Logic Diagram
23
Ssid/Ssvid
23
Device Serial Number Enhanced Capability
23
Pin Description
24
Table 1.3 General Purpose I/O Pins
25
Table 1.4 System Pins
25
Table 1.5 Test Pins
26
Table 1.6 Power and Ground Pins
26
Pin Characteristics
27
Table 1.7 Pin Characteristics
27
System Identification
28
Vendor ID
28
Device ID
28
Revision ID
28
Jtag ID
28
Port Configuration
28
Table 1.8 PES4T4 Device ID
28
Table 1.9 PES4T4 Revision ID
28
Figure 1.3 PES4T4 Port Configuration
29
Clocking, Reset, and Initialization
31
Introduction
31
Initialization
31
Figure 2.1 Common Clock on Upstream and Downstream
31
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream
32
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream
32
Figure 2.4 Non-Common Clock on Upstream and Downstream
33
Reset
34
Table 2.1 Boot Configuration Vector Signals
34
Fundamental Reset
35
Hot Reset
36
Figure 2.5 Fundamental Reset with Serial EEPROM Initialization
36
Upstream Secondary Bus Reset
37
Downstream Secondary Bus Reset
38
Downstream Port Reset Outputs
38
Power Enable Controlled Reset Output
38
Power Good Controlled Reset Output
39
Figure 2.6 Power Enable Controlled Reset Output Mode Operation
39
Figure 2.7 Power Good Controlled Reset Output Mode Operation
39
Hot Reset Controlled Reset Output
40
Theory of Operation
41
Port Interrupts
41
Legacy Interrupt Emulation
41
Table 3.1 Downstream Port Interrupts
41
Table 3.2 PES4T4 Downstream to Upstream Port Interrupt Routing
42
Link Operation
43
Introduction
43
Polarity Inversion
43
Link Width Negotiation
43
Link Retraining
43
Link down
43
Slot Power Limit Support
44
Upstream Port
44
Downstream Port
44
Link States
44
Active State Power Management
45
Figure 4.1 PES4T4 ASPM Link Sate Transitions
45
Link Status
46
General Purpose Inputs/Outputs
47
Introduction
47
GPIO Configuration
47
GPIO Pin Configured as an Input
47
Table 5.1 General Purpose I/O Pin Alternate Function
47
Table 5.2 GPIO Pin Configuration
47
GPIO Pin Configured as an Output
48
GPIO Pin Configured as an Alternate Function
48
Smbus Interfaces
53
Introduction
53
Master Smbus Interface
53
Initialization
53
Serial EEPROM
53
Table 6.1 PES4T4 Compatible Serial Eeproms
53
Figure 6.1 Single Double Word Initialization Sequence Format
54
Figure 6.2 Sequential Double Word Initialization Sequence Format
55
Figure 6.3 Configuration Done Sequence Format
55
Table 6.2 Serial EEPROM Initialization Errors
56
I/O Expanders
57
Table 6.3 I/O Expander Function Allocation
57
Table 6.4 I/O Expander Default Output Signal Value
58
Table 6.5 I/O Expander 0 Signals
60
Table 6.6 I/O Expander 1 Signals
61
Table 6.7 I/O Expander 2 Signals
62
Table 6.8 I/O Expander 4 Signals
62
Power Management
65
Introduction
65
Figure 7.1 PES4T4 Power Management State Transition Diagram
65
PME Messages
66
Table 7.1 PES4T4 Power Management State Transition Diagram
66
Power Express Power Management Fence Protocol
67
Power Budgeting Capability
67
Wakeup Protocol
68
WAKEN Signal as an Input
69
WAKEN Signal as an Output
69
WAKEN and Beacon Disabled
69
Auxiliary Power Implementation
69
Switch System States
69
Figure 7.2 PES4T4 System States
69
Auxiliary Power Control
70
Figure 7.3 L2 Mode Enable/Disable and Frsticky Bit Initialization
71
PES4T4 Auxiliary Power Usage
72
Figure 7.4 Vaux Usage Model
72
Table 7.2 Auxiliary Power Enabled (Beacon OFF)
73
Table 7.3 Auxiliary Power Enabled (Serdes OFF, Only WAKEN Enabled)
73
Figure 7.5 Conceptual Diagram of the PES4T4 Auxiliary Power Connection
74
Hot-Plug and Hot-Swap
75
Introduction
75
Figure 8.1 Hot-Plug on Switch Downstream Slots Application
75
Figure 8.2 Hot-Plug with Switch on Add-In Card Application
76
Figure 8.3 Hot-Plug with Carrier Card Application
76
Hot-Plug I/O Expander
78
Hot-Plug Interrupts and Wake-Up
78
Legacy System Hot-Plug Support
78
Figure 8.4 PES4T4 Hot-Plug Event Signalling
79
Hot-Swap
80
Configuration Registers
81
Table 9.1 Base Addresses for Port Configuration Space Registers
81
PCI Express Capability Structure
82
Figure 9.1 Port Configuration Space Organization
82
Table 9.2 Upstream Port 0 Configuration Space Registers
83
Table 9.3 Downstream Ports 2 through 5 Configuration Space Registers
87
Power Management Capability Structure
112
Message Signaled Interrupt Capability Structure
114
Subsystem ID and Subsystem Vendor ID
115
Extended Configuration Space Access Registers
116
Advanced Error Reporting (AER) Enhanced Capability
117
Device Serial Number Enhanced Capability
123
PCI Express Virtual Channel Capability
123
Power Budgeting Enhanced Capability
129
Switch Control and Status Registers
131
Internal Switch Error Control and Status Registers
140
Wakeup Protocol Registers
143
JTAG Boundary Scan
145
Introduction
145
Test Access Point
145
Signal Definitions
145
Figure 10.1 Diagram of the JTAG Logic
145
Table 10.1 JTAG Pin Descriptions
146
Figure 10.2 State Diagram of Pes4T4'S TAP Controller
146
Boundary Scan Chain
147
Table 10.2 Boundary Scan Chain
147
Test Data Register (DR)
148
Boundary Scan Registers
148
Figure 10.3 Diagram of Observe-Only Input Cell
148
Figure 10.4 Diagram of Output Cell
149
Figure 10.5 Diagram of Bidirectional Cell
149
Instruction Register (IR)
150
Extest
150
Table 10.3 Instructions Supported by Pes4T4'S JTAG Boundary Scan
150
Sample/Preload
151
Bypass
151
Clamp
151
Idcode
151
Table 10.4 System Controller Device Identification Register
151
Figure 10.6 Device ID Register Format
151
Validate
152
Reserved
152
Usage Considerations
152

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