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IDT

Tsi576

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Serial RapidIO Switch

User Manual

June 6, 2016

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Summary of Contents for Renesas IDT Tsi576

Page 1 Titl Tsi576   Serial RapidIO Switch User Manual June 6, 2016...
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT.
Page 3: Table Of Contents
Contents About this Document........... . 17 Scope .
Page 4 Contents Reset Control Symbol Processing ............. 57 Data Integrity Checking.
Page 5 Contents 4.2.1 Transfer Modes..............87 Arbitration for Egress Port .
Page 6 Contents 6.6.3 Servicing Port-writes ............. . 137 6.6.4 Port-writes and Hot Insertion/Hot Extraction Notification .
Page 7 Contents Error Handling ................176 7.10 Interrupt Handling .
Page 8 Contents 10.1.5 Clock Gating ..............210 10.2 Resets .
Page 9 Contents 12.6.3 RapidIO Switch Port General Control CSR..........274 12.6.4 RapidIO Serial Port x Link Maintenance Request CSR .
Page 10 Contents 12.9.5 RapidIO Port x Performance Statistics Counter 1 Register ....... . . 347 12.9.6 RapidIO Port x Performance Statistics Counter 2 Register .
Page 11 Contents 12.14.5 SerDes Lane 0 Pattern Matcher Control Register ........409 12.14.6 SerDes Lane 1 Pattern Matcher Control Register .
Page 12 Contents 13.2.35 I C Boot Load Diagnostic Progress Register ......... . . 483 13.2.36 I C Boot Load Diagnostic Configuration Register .
Page 13 Figures Figure 1: Block Diagram................22 Figure 2: Wireless Baseband Card .
Page 14 Figures Figure 43: Latency Illustration ............... . 190 Figure 44: Congestion and Detection Flowchart .
Page 15 Tables Table 1: Error Summary ................50 Table 2: Lookup Table States.
Page 16 Tables Table 43: Tundra-Specific Per-Port Performance Registers ..........333 Table 44: Tundra-Specific RapidIO Registers.
Page 17: About This Document
About this Document This section discusses the following topics: • “Scope” on page 17 • “Document Conventions” on page 17 • “Revision History” on page 18 Scope The Tsi576 User Manual discusses the features, capabilities, and configuration requirements for the Tsi576.
Page 18: Revision History
About this Document Object Size Notation • A byte is an 8-bit object. • A word is a 16-bit object. • A doubleword (Dword) is a 32-bit object. Numeric Notation • Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04). •...
Page 19 About this Document February 19, 2015, Formal • Updated the “Ordering Information” September 16, 2014, Formal • Updated step 2 in the “Hot Extraction” procedure • Added a new section, “Lane Sync Timer” • Updated “Power-Down Options” • Updated Figure 14: Drive Strength and Equalization Waveform •...
Page 20 About this Document Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 21: Functional Overview
C Interface” on page 30 • “JTAG Interface” on page 32 Overview The IDT Tsi576 is a third-generation RapidIO switch family supporting 40 Gbits/s aggregate bandwidth. The Tsi576 enables customers to develop systems with robust features and high performance at low cost.
Page 22: Typical Applications
1. Functional Overview > Overview Figure 1: Block Diagram Multicast Engine (1x) (1x) (1x) (1x) (1x) (1x) Internal Switching Fabric (1x) (1x) SP10 SP12 (4x or 1x) (4x or 1x) SP11 SP13 (1x) (1x) Registers I 2 C JTAG 80B804A_BK001_02 Master and IEEE1149.6 Boundary Scan Slave Devices...
Page 23: Figure 2: Wireless Baseband Card
1. Functional Overview > Overview Figure 2: Wireless Baseband Card Power MPC8560 MPC8560 FPGA T si576 QUICC III 80B804A_TA001_01 In video infrastructure cards, equipment vendors must maximize the number of DSPs per card to manage compression and decompression algorithms. These DSPs are controlled by a local processor and all these components are linked together by a low power, small form factor, low latency, multicast enabled Tsi576.
Page 24: Features
1. Functional Overview > Overview 1.1.2 Features The Tsi576 contains the following features: Electrical Layer Serial RapidIO Features • Up to 2 ports in 4x Serial mode • Up to 12 ports in 1x Serial mode • Operating baud rate per data lane: 1.25 Gbit/s, 2.5 Gbit/s, or 3.125Gbit/s •...
Page 25 1. Functional Overview > Overview • 10 Gbit/s of instantaneous multicast input bandwidth • Packets are replicated to each egress port in parallel • The multicast engine can accept a bursts of traffic with different packet sizes • Arbitration at the egress port to allow management of resource contention between multicast or non-multicast traffic.
Page 26: Serial Rapidio Interface
1. Functional Overview > Serial RapidIO Interface Serial RapidIO Interface The Tsi576 provides high-performance serial RapidIO interfaces that are used to provide connectivity for control plane and data plane applications. All RapidIO interfaces are compliant with the RapidIO Interconnect Specification (Revision 1.3). This section describes the transport layer features common to all Tsi576 RapidIO interfaces.
Page 27: Maintenance Requests
1. Functional Overview > Multicast Engine The packet transmitter and the packet receiver cooperate to ensure that packets are never dropped (lost). A transmitter must retain a packet in its buffers until the port receives a packet accepted control symbol from the other end of the link. 1.2.3 Maintenance Requests A maintenance packet is the only packet type that will be modified by the switch.
Page 28: Serial Rapidio Electrical Interface
1. Functional Overview > Serial RapidIO Electrical Interface The Tsi576 includes the following features: • One multicast engine provides dedicated multicast resources without impacting throughput on the ports • Eight multicast groups • Sustained multicast output bandwidth, up to 10 Gbit/s per egress port •...
Page 29: Figure 4: Tsi576 Mac Block Diagram
1. Functional Overview > Serial RapidIO Electrical Interface Figure 4: Tsi576 MAC Block Diagram Serial Rapid IO Registers and Buffers Numbered Even-numbered Ports (4x mode or 1x mode) Ports (1x mode only) 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B PRBS PRBS PRBS...
Page 30: Internal Switching Fabric (Isf)
1. Functional Overview > Internal Switching Fabric (ISF) Internal Switching Fabric (ISF) The Internal Switching Fabric (ISF) is the crossbar switching matrix at the core of the Tsi576. It transfers packets from ingress ports to egress ports and prioritizes traffic based on the RapidIO priority associated with a packet and port congestion.
Page 31 1. Functional Overview > I C Interface — I C Interface: Master interface – Supports 7-bit device addressing – Supports 0, 1, or 2-byte peripheral addressing – Supports 0, 1, 2, 3, or 4-byte data transfers – Reverts to slave mode if arbitration is lost –...
Page 32: Jtag Interface
1. Functional Overview > JTAG Interface • CBUS compatibility — Tsi576 does not provide the DLEN signal — Tsi576 does not respond as a CBUS device when addressed with the CBUS address. The Tsi576 will interpret the CBUS address like any other 7-bit address and compare it to its device address without consideration for any other meaning.
Page 33 1. Functional Overview > JTAG Interface — Bypass — Hi-Z — IDCODE — Clamp — User data select Integrated Device Technology Tsi576 User Manual www.idt.com June 6, 2016...
Page 34 1. Functional Overview > JTAG Interface Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 35: Serial Rapidio Interface
Serial RapidIO Interface This chapter describes the serial RapidIO interface of the Tsi576. It includes the following information: • “Overview” on page 35 • “Transaction Flow” on page 37 • “Lookup Tables” on page 37 • “Maintenance Packets” on page 53 •...
Page 36: Transaction Flow Overview
2. Serial RapidIO Interface > Overview • Proprietary registers for performance monitoring and tuning • Both cut-through and store-and-forward modes for performance tuning • Debug packet generation and capture • Multicast functionality (described in RapidIO Interconnect Specification (Revision 1.3) Part 11) •...
Page 37: Transaction Flow
2. Serial RapidIO Interface > Transaction Flow Transaction Flow The Tsi576 receives a RapidIO packet on one of its RapidIO ports. After performing integrity checks, such as validating a CRC, the interface logic locates the destination ID in the packet. The Tsi576 uses this information to determine to which egress port the packet must be sent and whether it is a multicast packet.
Page 38: Filling The Lookup Tables
2. Serial RapidIO Interface > Lookup Tables The LUTs support two modes of operation, selectable on a per-port basis: “Flat Mode” on page 40 “Hierarchical Mode” on page 45. Flat mode is the default mode and it supports destination IDs in the range of 0 to 511, with a default port for destination IDs outside this range.
Page 39: Figure 5: Lut Mode Of Operation
2. Serial RapidIO Interface > Lookup Tables Figure 5: LUT Mode of Operation Start Flat LUT_512 = 1 in the SPx_MODE register Heirarchical 8 bit (TT=0) Width of DestID DestID < 256 16 bit (TT=1) MSB of DestID[15:8] == DestID < 512 BASE field in SPx_ROUTE_BASE Obtain egress port...
Page 40: Lut Modes
2. Serial RapidIO Interface > Lookup Tables 2.3.2 LUT Modes The LUT mode, flat or hierarchical, is selected on a per-port basis through the LUT_512 field value in “RapidIO Port x Mode CSR” on page 312. 2.3.3 Flat Mode A flat mode LUT is a table that maps destination IDs 0 to 511 to user selectable egress ports. Destination IDs that fall outside this range are sent to the egress port identified in the RIO Route LUT Attributes CSR (see “RapidIO Route LUT Attributes (Default Port)
Page 41: Figure 6: Flat Mode Routing
2. Serial RapidIO Interface > Lookup Tables Figure 6: Flat Mode Routing Global LUT DestID Port DestID MSB is loaded into Global LUT through the LRG_CFG_DEST_ID and CFG_DEST_ID fields in the RIO_ROUTE_CFG_DESTID register Egress Port is loaded into the Global LUT through the PORT field in the RIO_ROUTE_CFG_PORT register Local LUT...
Page 42: Figure 7: Flat Mode Routing Example
2. Serial RapidIO Interface > Lookup Tables Figure 7 shows an example of flat mode operation. Figure 7: Flat Mode Routing Example DestIDs accessible through this link = 0x02xx to 0xFFxx DestIDs accessible through this link = 0x01xx Tsi57x Tsi57x DestID = 0x13 Ingress Packets DestID = 0x11...
Page 43: Figure 8: Flat Mode Lut Configuration Example
2. Serial RapidIO Interface > Lookup Tables 2.3.3.1 Flat LUT Programming Each of the ports on the Tsi576 has its own lookup table. Each lookup table can be programmed with different values which allows each port to route packets differently. The lookup table maps the packet to the correct output port based on the destination ID.
Page 44 2. Serial RapidIO Interface > Lookup Tables • “RapidIO Port x Route Config Output Port CSR” on page 317 • “RapidIO Port x Local Routing LUT Base CSR” on page 318 Other indirectly related (multicast) registers include: • “RapidIO Multicast Mask Configuration Register” on page 265 •...
Page 45: Hierarchical Mode
2. Serial RapidIO Interface > Lookup Tables Example Two: Adding a Lookup Table Entry In the following example, routing is added for port 0x5 to route destination ID 0x20 to output port 0x3. To add a lookup table, complete the following steps: 1.
Page 46: Figure 9: Hierarchical Mode
2. Serial RapidIO Interface > Lookup Tables If the result of a lookup yields an egress port number greater than the value in PORT_TOTAL (“RapidIO Switch Port Information CAR” on page 254), the incoming packet is routed to the Default Port defined by “RapidIO Route LUT Attributes (Default Port) CSR”.
Page 47: Figure 10: Hierarchical Mode Routing Example
2. Serial RapidIO Interface > Lookup Tables Figure 10: Hierarchical Mode Routing Example DestIDs accessible through DestIDs accessible through this link = 0xFExx, 0xFFxx this link = 0x02xx, 0x01xx, 0x00xx Tsi57x Tsi57x DestID = 0x2813 Ingress Packets DestID = 0x2811 DestID = DestID = Tsi57x...
Page 48 2. Serial RapidIO Interface > Lookup Tables 2.3.4.1 Hierarchical LUT Programming This example demonstrates the process used to program the LUT in Hierarchical mode and uses Figure 10 for reference. The following example shows how to program the LUT in Port 8, but because all ports in the Tsi576 are capable of operating in hierarchical mode, this procedure can be easily modified to accommodate a different ingress port.
Page 49: Mixed Mode Of Operation
2. Serial RapidIO Interface > Lookup Tables 5. Program the Local LUT with the LSB values corresponding to an MSB of 0x28xx. W 11870 0x2810 W 11874 0x3 W 11870 0x2811 W 11874 0x1 W 11870 0x2812 W 11874 0x2 W 11870 0x2813 W 11874 0x0 2.3.5...
Page 50: Lookup Table Error Summary
2. Serial RapidIO Interface > Lookup Tables 2.3.7 Lookup Table Error Summary Table 1 summarizes error conditions and resulting behaviors associated with the LUTs. Table 1: Error Summary Event Behavior Packet routed to a shut down port Packet discarded and no record of packet is kept Packet routed to disabled port ISF time out occurs and a transaction error acknowledge (TEA) interrupt is asserted (if enabled)
Page 51: Lookup Table Entry States
2. Serial RapidIO Interface > Lookup Tables If a LUT entry is unmapped for a particular port or the destination ID does not match any of the LUT entry, packets are routed to the default output port, as defined by “RapidIO Port x Route Config DestID CSR”...
Page 52 2. Serial RapidIO Interface > Lookup Tables Table 2: Lookup Table States Lookup Table Entry State How to get into States Action on Packet Arrival Parity Error When a lookup table entry’s parity is incorrect, the • Packet Header recorded in error capture lookup table entry is in a parity error state.
Page 53: Maintenance Packets
2. Serial RapidIO Interface > Maintenance Packets Maintenance Packets Maintenance packets are handled differently than other packets by the Tsi576. In a system the Tsi576 can be the destination of the maintenance packet. Maintenance packet processing is based on the maintenance packet’s hop count value. The hop count value controls how many hops the maintenance packet travels before it reaches its destination.
Page 54 2. Serial RapidIO Interface > Maintenance Packets Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi576 Responses Transaction Type Size Field Action taken by Tsi576 Error Logging Notes Write Request Do not care Send Maintenance Erred Write Request with no payload Response with Status...
Page 55: Multicast Event Control Symbols
2. Serial RapidIO Interface > Multicast Event Control Symbols Multicast Event Control Symbols Multicast-Event Control Symbol (MCS or MCES) forwarding describes the process where an MCS received on one RapidIO port is propagated out other RapidIO ports. When a RapidIO port receives an MCS, it signals all other ports of the fact that an MCS was received. Each port can optionally transmit an MCS when it is notified that an MCS has been received by another port.
Page 56: Generating An Mcs
2. Serial RapidIO Interface > Multicast Event Control Symbols 2.5.2 Generating an MCS The Tsi576 supports the generation of an MCS in two ways. The first method is called the software usage model which use of a maintenance write transaction in a port (see “RapidIO Port x Send Multicast-Event Control Symbol Register”...
Page 57: Reset Control Symbol Processing
2. Serial RapidIO Interface > Reset Control Symbol Processing Reset Control Symbol Processing One of the functions that can be performed by control symbols is requesting that the link partner reset itself. The Tsi576 can generate link-request/reset control symbols using the standard RapidIO registers defined for the purpose.
Page 58: Software Assisted Error Recovery
2. Serial RapidIO Interface > Error Management 2.8.1 Software Assisted Error Recovery The software-assisted error recovery process is described in terms of the ackIDs of a Tsi576 port connected to a link partner that becomes mismatched. A system host , which can be local or remote to the Tsi576 switch, has access to the device through another port.
Page 59: Hot Insertion And Hot Extraction
2. Serial RapidIO Interface > Hot Insertion and Hot Extraction Hot Insertion and Hot Extraction Hot insertion and hot extraction functionality enables reliable systems to safely add, remove, and replace components while the system continues to operate. The system host can use the Tsi576’s capability to restrict the access of a newly inserted component to prevent a faulty component from negatively affecting the system.
Page 60: Hot Insertion
2. Serial RapidIO Interface > Hot Insertion and Hot Extraction 2.9.1 Hot Insertion When Hot Insertion occurs at Port#N, the following steps should be completed: 1. Power up the Port#N in Tsi576. 2. Lock out Port#N by writing 1 to PORT_LOCKOUT in “RapidIO Serial Port x Control CSR”.
Page 61: Hot Extraction
2. Serial RapidIO Interface > Hot Insertion and Hot Extraction As with a controlled reset of a link partner (see “Generating a RapidIO Reset Request to a Peer Device”), the writes of the two OUTBOUND values must occur in the order given (for example, the Tsi576 followed by the link partner).
Page 62: Hot Extraction System Notification
2. Serial RapidIO Interface > Loss of Lane Synchronization 2.9.3 Hot Extraction System Notification System designers may require confirmation of when a component is extracted. The following sections describe the confirmation methods supported by the Tsi576. 2.9.3.1 Polling The system can poll the PORT_OK and PORT_UNINIT bits in the “RapidIO Port x Error and Status CSR”...
Page 63: Figure 11: Lols Silent Period
2. Serial RapidIO Interface > Loss of Lane Synchronization Figure 11 shows the Tsi576 entering the silence period when it experiences the loss of signal from its link partner. Figure 11: LOLS Silent Period Once synchronization is re-acquired, the Tsi576 transmitter resumes all timers and resumes sending packets from the next un-sent packet in its transmit queue, using the next available ackID.
Page 64: Dead Link Timer
2. Serial RapidIO Interface > Loss of Lane Synchronization 2.10.1 Dead Link Timer When a LOLS event occurs, the loss of communication can continue for an extended length of time. For example, there may be an uncontrolled extraction of the link partner, and a hardware fault on the link partner.
Page 65: Serial Rapidio Electrical Interface
Serial RapidIO Electrical Interface This chapter describes the IDT-specific electrical layer features of the Tsi576 Serial RapidIO Electrical Interface. See the “Serial RapidIO Interface” for a description of the standards-defined RapidIO features common to all RapidIO ports. This chapter includes the following information: •...
Page 66: Figure 12: Tsi576 Mac Block Diagram
3. Serial RapidIO Electrical Interface > Overview Figure 12: Tsi576 MAC Block Diagram Serial Rapid IO Registers and Buffers Numbered Even-numbered Ports (4x mode or 1x mode) Ports (1x mode only) 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B PRBS PRBS PRBS PRBS...
Page 67: Port Numbering
3. Serial RapidIO Electrical Interface > Port Numbering Port Numbering The RapidIO ports on the Tsi576 are numbered sequentially from 0 to 13. The following table shows the mapping between port numbers and the physical ports. These port numbers are used within the destination lookup tables for ingress RapidIO ports and in numerous register configuration fields.
Page 68: Port Configuration
3. Serial RapidIO Electrical Interface > Port Aggregation: 1x and 4x Modes Table 4: Tsi576 Port Numbering Port Number RapidIO Port Mode Note Serial Port 14 (SP14) Unavailable This port is un-initialized and the port registers must be treated as reserved. Writes to port registers can cause undefined behavior and is not recommended.
Page 69: 1X + 1X Configuration
3. Serial RapidIO Electrical Interface > Port Aggregation: 1x and 4x Modes • Port N can operate in 4x while port N+1 is unused and can be powered down (the 4x + 0x configuration) 1x mode means that one physical SerDes lane is used between link partners, and 4x mode means that four physical lanes are used between link partners.
Page 70: Configuration
3. Serial RapidIO Electrical Interface > Clocking 3.3.2 4x Configuration When the even-numbered port in a Tsi576 MAC is configured to operate in 4x mode (for example port 0), the odd-numbered port in a MAC (for example port 1) cannot be used and the register values for the odd-numbered port should be ignored.
Page 71: Changing The Clock Speed
3. Serial RapidIO Electrical Interface > Clocking The Tsi576 uses only one external differential clock source (S_CLK_P/N) as the reference to generate all internal clocks for processing the data. When the frequency of the reference clock is set at 156.25 MHz, Tsi576 can support three different RapidIO standard signaling rates (3.125 Gbps, 2.5 Gbps, and 1.25 Gbps).
Page 72: Changing The Clock Speed Through I
3. Serial RapidIO Electrical Interface > Port Power Down For more information about powering down ports and special requirements for powering down port 0, “Port Power Down” on page 3.4.2 Changing the Clock Speed Through I The Tsi576 can be configured to power up with ports at different link speeds by setting the “SRIO MAC x Digital Loopback and Clock Selection Register”...
Page 73: Default Configurations On Power Down
3. Serial RapidIO Electrical Interface > Port Power Down • “Internal Switching Fabric (ISF) Registers” • “I2C Registers” on page 417 • “Utility Unit Registers” on page 390 3.5.1 Default Configurations on Power Down When a port is powered down, the port loses configuration information that is stored for that specific port.
Page 74: Power-Down Options
3. Serial RapidIO Electrical Interface > Port Power Down 3.5.3 Power-Down Options The following power-down options are available on a port: • A port’s main logic can be powered down at boot up through the SP{n}_PWRDN pins. • The default configuration provided by the pins can be changed using the PWDN_X4 and PWDN_X1 bits in the “SRIO MAC x Digital Loopback and Clock Selection Register”.
Page 75: Port Lanes
3. Serial RapidIO Electrical Interface > Port Lanes 3.5.4.1 Signals Sampled After Reset After a hardware reset is de-asserted, the Tsi576 samples the state of the SP{n}_PWRDN pins and only powers up the ports that are enabled. Each RapidIO port has a unique pin, SPn_PWRDN. Port 0 is the default port and can only be powered down through a direct register write.
Page 76: Lane Swapping
3. Serial RapidIO Electrical Interface > Port Lanes 3.6.2 Lane Swapping Lane swap is the ability to reverse the order of the transmit and receive pins. The Tsi576 allows the order of the transmit and/or receive pins of each 4x port to be reversed in order to simplify board layout issues.
Page 77: Programmable Transmit And Receive Equalization
3. Serial RapidIO Electrical Interface > Programmable Transmit and Receive Equalization Channels are numbered 0 through 3. Channels are never reordered. When lanes are not swapped, the following mapping between channels and lanes is used: • Channel 0 maps to Lane A •...
Page 78: Receive Equalization
3. Serial RapidIO Electrical Interface > Programmable Transmit and Receive Equalization The drive strength current of each lane can be controlled through the TX_LVL field in the “SRIO MAC x SerDes Configuration Global” on page 374, and the TX_BOOST field in the “SRIO MAC x SerDes Configuration Channel 0”...
Page 79: Port Loopback Testing
3. Serial RapidIO Electrical Interface > Port Loopback Testing Port Loopback Testing The Tsi576’s serial RapidIO ports support the following kinds of loopback: • Digital equipment loopback • Logical line loopback Figure 15 shows where each loopback is implemented in the Tsi576. Figure 15: Tsi576 Loopbacks More RapidIO Ports Internal Switching Fabric...
Page 80: Digital Equipment Loopback
3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) 3.8.1 Digital Equipment Loopback Digital equipment loopback is enabled on a per-port basis through the “SRIO MAC x Digital Loopback and Clock Selection Register” on page 379. When this form of loopback is enabled, the serial port transmit logic is connected to the receive logic just before the 8B/10B encoder and transmitter.
Page 81 3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) Table 8: Patterns Supported by Generator MODE Setting Description 2 byte DC balanced pattern constructed as {PAT0, ~PAT0} 4 byte DC balanced pattern constructed as: {0x000, PAT0, 0x3FF, ~PAT0} Reserved BERT testing is enabled on a per-bit lane basis, and normal traffic flow on the bit lane ceases when BERT testing is enabled.
Page 82: Bert Pattern Matcher And Error Counter
3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) 3.9.2 BERT Pattern Matcher and Error Counter The pattern matcher is capable of synchronizing to and detecting erroneous bytes in the two LFSR patterns mentioned in Table 9. Erroneous bytes are counted in the error counter in the “SerDes Lane 0 Pattern Matcher Control Register”...
Page 83: Using Prbs Scripts For The Transmitters And Receivers
3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) — 3.9.3.1 Fixed Pattern-based BERT Transmitter Configuration To configure a Tsi576 transmitter for fixed-pattern BERT operation: • Write the bit stream to be transmitted into the PAT0 field in the “SerDes Lane 0 Pattern Generator Control Register”...
Page 84 3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 85: Internal Switching Fabric
Internal Switching Fabric This chapter describes the main features and functions of the Tsi576’s Internal Switching Fabric (ISF). It includes the following information: • “Overview” on page 85 • “Functional Behavior” on page 86 • “Arbitration for Egress Port” on page 88 Overview The Internal Switching Fabric (ISF) is the crossbar switching matrix at the core of the Tsi576.
Page 86: Functional Behavior
4. Internal Switching Fabric > Functional Behavior Functional Behavior The ISF is responsible for transporting packets from an ingress port to an egress port and to and from the multicast engine. When RapidIO packets arrive at the ingress ports, the Tsi576 performs several tests to ensure the packet is valid.
Page 87: Transfer Modes
4. Internal Switching Fabric > Functional Behavior 4.2.1 Transfer Modes The ISF supports both cut-through and store-and-forward transfer modes. These modes are selectable on a per-port basis. By default, all ports are configured for store-and-forward mode. To change the configuration, write the TRANS_MODE field in the “RapidIO Port x Control Independent Register”...
Page 88: Arbitration For Egress Port
4. Internal Switching Fabric > Arbitration for Egress Port Arbitration for Egress Port When multiple ingress ports need to send a packet to the same egress port at the same time, the egress port must make an arbitration decision about which packet to accept. An output arbiter exists for each egress port.
Page 89: Weighted Round Robin (Wrr) Arbitration
4. Internal Switching Fabric > Arbitration for Egress Port Priority 3 packets from a given port are always transmitted when the port has its turn. However, priority 2 or lower priority packets may not be sent to an egress port when the number of free buffer associated with that particular port is equal or smaller than the watermark for that particular priority.
Page 90: Table 10: Sample Register Settings For Wrr In A Given Priority Group (Wrr_En=1)
4. Internal Switching Fabric > Arbitration for Egress Port When weighted operation is required, WRR_EN is asserted (WRR_EN=1). Then the type and quantity of preferred traffic is selected by programming the CHOOSE_UC bit and the minimum number of packets allocated for the chosen traffic on the egress port using the WEIGHT field in the “Port x Prefer Unicast and Multicast Packet Prio 0 Register”...
Page 91: Packet Queuing
4. Internal Switching Fabric > Packet Queuing Packet Queuing The Tsi576 has a queuing system on both the ingress and egress ports. Figure 19: Ingress and Egress Packet Queues in Tsi576 Ingress Egress Packet Queue Packet Queue 4.4.1 Output Queuing on the Egress Port Each egress port has a queue that holds up to eight packets.
Page 92 4. Internal Switching Fabric > Packet Queuing 4.4.1.1 Egress Watermark The ISF egress arbiter generates flow control for a given priority of traffic based on watermarks. Watermarks are defined for priority 0, 1, and 2 packets (no watermark is defined for priority 3 packets because they are always accepted whenever there are free buffers).
Page 93: Table 11: Examples Of Use Of Watermarks
4. Internal Switching Fabric > Packet Queuing Two examples are given in Table 11. The first example describes the default setting of the three watermarks. This maximizes the number of buffers that can accept lower priority packets, which maximizes the throughput of these priorities. The second example describes a customized setting which favors the priority 3 and 2 traffic at the expense of the throughput of priority 1 and 0 packets.
Page 94: Input Queue For The Isf Port
4. Internal Switching Fabric > Packet Queuing 4.4.1.2 Transmitting Packets from the Egress Port to the Link Partner Packets in the output queue are transmitted on the RapidIO link in first-come, first-served (FCFS) order (except during re-transmission). Retransmission represents an opportunity for reordering operations as described in input arbitration (see “Input Queue for the ISF Port”...
Page 95: Input Arbitration
4. Internal Switching Fabric > Packet Queuing In some systems, it is necessary to guarantee maximum throughput for a burst (continuous sequence) of packets at the same priority. In a congested system, it is possible that only one buffer is available for these packets.
Page 96 4. Internal Switching Fabric > Packet Queuing 4.4.3.1 First Come, First Served Mode In this mode, packets flow through the ingress queues in order unless reordering is required to manage head-of-line blocking. The packet closest to the head of the queue that can make progress is selected to make progress regardless of its priority.
Page 97 4. Internal Switching Fabric > Packet Queuing 4.4.3.3 Strict Priority Two In this mode, higher priority packets are served ahead of lower priority packets, even when the high priority packets are blocked. This mode has decreased throughput, but does have the lowest latency on high priority packets.
Page 98 4. Internal Switching Fabric > Packet Queuing Reorder limiting prevents excessive delays of a packet by packets of lower or equal priority. Reorder limiting does not prevent delays of a packet by packets of higher priority. When reorder limiting is enabled, each time a packet X is delayed in the queue because a lower or same priority packet was sent earlier, the fabric decrements the reorder counter.
Page 99: Input Queuing Model For The Multicast Work Queue
4. Internal Switching Fabric > Packet Queuing 4.4.3.5 Transaction Error Acknowledge (TEA) A Transaction Error Acknowledge signal is implemented in the ISF request queue to control the time a packet can be at the head of the request queue. When an ingress packet at the head of the request queue sends a request to the ISF, a timer is started to keep track of the request time.
Page 100: Input Queuing Model For The Broadcast Buffer
4. Internal Switching Fabric > Packet Queuing 4.4.5 Input Queuing Model for the Broadcast Buffer The broadcast buffer receives data from only one source - the multicast work queue. The broadcast buffer operates in strict First-In, First-Out (FIFO) order. The broadcast buffer does not use watermarks.
Page 101 4. Internal Switching Fabric > Packet Queuing Bandwidth can be wasted during transfers in cut through mode. If the ingress port operates at a slower rate than the egress port, the egress port receives idles whenever the ingress port has not yet received data for transmission.
Page 102 4. Internal Switching Fabric > Packet Queuing Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 103: Multicast
Multicast This chapter describes the multicast features of the Tsi576. It includes the following information: • “Overview” on page 103 • “Multicast Behavior Overview” on page 106 • “Multicast Group Tables” on page 110 • “Multicast Work Queue” on page 107 •...
Page 104: Multicast Operation With Multiple Tsi57X Switches
5. Multicast > Overview The Tsi576 includes the following features: • One multicast engine provides dedicated multicast resources without impacting throughput on the ports • Eight multicast groups • Sustained multicast output bandwidth, up to 10 Gbit/s per egress port •...
Page 105: Multicast Terminology
5. Multicast > Overview For systems that use multiple Tsi57x switches, the multicast engine (MCE) in each switch can be used provided that multicast packets are not sent between the switches. This can be accomplished by having the multicast source program the MCE in the switch it is directly connected to (see step 1 in Figure 21), and then initiate an additional unicast transaction to the MCE in the other switch (see step 2).
Page 106: Multicast Behavior Overview
5. Multicast > Overview 5.1.5 Multicast Behavior Overview The multicast operation involves the following blocks: • Multicast Engine • Multicast Group Table • Multicast Work Queue • Broadcast Buffer for each egress port • ISF ingress arbitration algorithms for the Multicast Port •...
Page 107: Multicast Work Queue
5. Multicast > Overview 5.1.6 Multicast Work Queue The multicast work queue accepts packets from ingress ports and forwards them to the broadcast buffers according to the multicast group table. The multicast work queue can store a maximum of 2208 bytes of packet data or seven maximum sized packets inside its buffer.
Page 108: Figure 22: Multicast Packet Flow In The Tsi576
5. Multicast > Overview Once the egress port acknowledges the broadcast buffer’s request, the broadcast buffer transmits datums to the egress port at sustained rates of up to 10 Gbits/s . The egress port receives the broadcast buffers data, and can start to transmit that data as soon as the first datum is received. In RapidIO technology, a datum means a word of data sent in a single clock cycle.
Page 109 5. Multicast > Overview Description of events in the figure: 1. Port 1 receives a packet and consults its multicast group table. It determines that the packet is a multicast packet by examining the packet’s destination ID and TT fields. The packet ackID field is overwritten with the ingress port identifier.
Page 110: Multicast Group Tables
5. Multicast > Multicast Group Tables 9. Once in the egress buffer, the packet copies are subjected to STOMP (“Multicast Packet Stomping” on page 120), and packet reordering. The packet copies at each egress ports are transmitted out from the egress buffer independent of each port. When packets are being transferred in cut-through mode, it is possible for the packet to have an error detected in it (that is, CRC), or for the packet to be STOMPed by the RapidIO link partner.
Page 111 5. Multicast > Multicast Group Tables 3. Write the “RapidIO Multicast DestID Association Register” on page 268, setting the LARGE field to indicate whether the destination ID is an 8-bit or a 16-bit ID; and setting the CMD field to 11. This associates the destination ID to the list of ports that must receive copies of the packet.
Page 112: Configuring Basic Associations
5. Multicast > Multicast Group Tables Figure 23: Relationship Representation Switch Port Number Operating Mode 4x/1x/Power-down (PD) 4x N/A Multicast DEST_ID 0 = No Group Port Participating in Vector 1 = Yes Large Small Number Multicast Group Table Multicast Vector Table Configured using the Association between Multicast Group Number RIO Multicast DestID...
Page 113: Configuring Multicast Masks
5. Multicast > Multicast Group Tables 2. Associate destination ID 0x1234 with multicast mask 0 • Write the value 0x0000_00E0 to the “RapidIO Multicast DestID Association Register” on page 268 3. Set up the operation to associate destination ID 0x44 with multicast mask 1 •...
Page 114: Figure 24: Completed Tables At The End Of Configuration
5. Multicast > Multicast Group Tables 3. Add port 3 to multicast mask 1 • Write the value 0x0001_0310 to the Multicast Mask Configuration Register 4. Add port 4 to multicast mask 1 • Write the value 0x0001_0410 to the Multicast Mask Configuration Register 5.
Page 115 5. Multicast > Multicast Group Tables 5.2.2.3 Removing a Port from a Multicast Mask In this example, the device attached to port four must be removed from the system. The following register accesses are used to modify multicast masks one and two to stop port four from being a multicast destination: The accesses to the “RapidIO Multicast Mask Configuration Register”...
Page 116: Configuring Multicast Masks Using The Idt Specific Registers
5. Multicast > Multicast Group Tables 7. Verify that port 6 is included in mask 2 • Write the value 0x0002_0600 to the Multicast Mask Configuration Register • Read the value 0x0002_0601 from the Multicast Mask Configuration Register 8. Verify that port 7 is included in mask 2 •...
Page 117: Figure 25: Idt-Specific Multicast Mask Configuration
5. Multicast > Multicast Group Tables Figure 25: IDT-specific Multicast Mask Configuration Switch Port Number Multicast DEST_ID 0 = No Mask Port Participating in Vector 1 = Yes Large Small Number 0x10320 0x10300 0x10324 0x10304 0x10328 0x10308 0x1030C 0x1032C 0x10330 0x10310 0x10334 0x10314...
Page 118: Arbitration For Multicast Engine Ingress Port
5. Multicast > Arbitration for Multicast Engine Ingress Port Figure 26: Tundra-specific Multicast Mask Configuration Switch Port Number Multicast DEST_ID 0 = No Mask Port Participating in Vector 1 = Yes Large Small Number 0x10300 0x10320 0x10324 0x10304 0x10328 0x10308 0x1030C 0x1032C 0x10330...
Page 119: Figure 27: Arbitration Algorithm For Multicast Port
5. Multicast > Arbitration for Multicast Engine Ingress Port Figure 27: Arbitration Algorithm for Multicast Port Src Port 0 Packet Src Port 1 Packet Priority 3 Packets Src Port 13 Packet Src Port 0 Packet Src Port 1 Packet Priority 2 Packets Src Port 15 Packet Arbitration Result...
Page 120: Error Management Of Multicast Packets
5. Multicast > Error Management of Multicast Packets Error Management of Multicast Packets Multicast packets have four sources of error - packet TEA, packet STOMPing, exceeding the maximum latency time, and exceeding the time-to-live timeout. 5.4.1 Packet TEA A multicast packet at the head of the ingress queue is subject to TEA. The TEA function does not differentiate between multicast and unicast packets.
Page 121: Silent Discard Of Packets
5. Multicast > Error Management of Multicast Packets Once a packet is completely received in the broadcast buffer, the multicast latency timer starts counting. If the multicast latency timer expires while the packet is in the broadcast buffer, an interrupt is raised (see “RapidIO Broadcast Buffer Maximum Latency Expired Error Register”...
Page 122: Port-Writes And Multicast
5. Multicast > Port Reset 5.4.5 Port-writes and Multicast Port-writes can be multicast to multiple output links, depending on the destinationID of the port-write. Using the multicast feature improves the likelihood of delivery of port-writes for link failures. If a blocked or failed port becomes unblocked, port-writes may be delivered late. Port Reset When a port is powered down, the port looses configuration information that is stored for that particular port.
Page 123: Event Notification
Event Notification This chapter describes the system of error and event notification in the Tsi576. It includes the following information: • “Overview” on page 123 • “Event Summary” on page 124 • “Error Rate Thresholds” on page 128 • “Error Stopped State Recovery” on page 130 •...
Page 124: Event Summary
6. Event Notification > Event Summary Event Summary Table 13 describes all the events that can be raised within the Tsi576 and whether these events generate a interrupt, a port-write, or both. Table 13: Tsi576 Events Interface Where Event Name Event Generate Generate...
Page 125 6. Event Notification > Event Summary Table 13: Tsi576 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write Error Rate Error This event occurs when the error rate counter in the RapidIO Degraded “RapidIO Port x Error Rate CSR”...
Page 126 6. Event Notification > Event Summary Table 13: Tsi576 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write TEA in Fabric Error This event is raised when a fabric transmission request times out and a packet is dropped. (Output Drop) The status of this event is contained in the TEA bit of the “RapidIO Port x Interrupt Status Register”...
Page 127 6. Event Notification > Event Summary Table 13: Tsi576 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write Illegal AckID Error This event is raised when a RapidIO port receives a packet RapidIO in Packet with an ackID that is not in sequence.
Page 128: Error Rate Thresholds
6. Event Notification > Error Rate Thresholds Table 13: Tsi576 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write Control Error This event is raised when a RapidIO port receives a RapidIO Symbol Not “Packet-Not-Accepted”...
Page 129: Maintaining Packet Flow
6. Event Notification > Error Rate Thresholds — When the degraded threshold is hit, the Error Rate Degraded Threshold Reached event is raised. The port can be configured to raise an interrupt or issue a Port-write (or both). Another degraded event is not raised until the counter falls below the threshold and then reaches it again, due to subsequent errors.
Page 130: Error Stopped State Recovery
6. Event Notification > Error Stopped State Recovery • Multicast — If the multicast engine attempts to transfer a packet copy to a broadcast buffer but the buffer is full and unable to accept the packet, the MC_TEA is asserted in the congested port's “RapidIO Port x Interrupt Status Register”...
Page 131: Link Error Clearing And Recovery
6. Event Notification > Error Stopped State Recovery The following examples are Stype 1 errors: • Packet with an unexpected ackID value • Packet with an incorrect CRC value • Packet containing invalid characters or valid non-data characters • Packet that overruns some defined boundary such as the maximum data payload. Refer to error section (Part 6, Chapter 5, section 5.11) of the RapidIO Interconnect Specification (Revision 1.3) and “RapidIO Error Management Extension Registers”...
Page 132: Figure 29: Control Symbol Format
6. Event Notification > Error Stopped State Recovery Figure 29 shows the RapidIO standard packet-retry control symbol format. Figure 29: Control Symbol Format bits stype0 parameter0 parameter1 stype1 The IDT-specific functionality and control symbols process of using multiple control symbols in error clearing and recovery uses the following control symbols: •...
Page 133: Event Capture
6. Event Notification > Event Capture Event Capture When a notification-enabled RapidIO error occurs, the port where the error occurred also logs information about the packet that caused the event. This information is stored within the RapidIO Packet Error Capture registers (see “RapidIO Error Management Extension Registers”...
Page 134: Table 14: Error Rate Error Events
6. Event Notification > Event Capture For more detail on these events, see the RapidIO Interconnect Specification (Revision 1.3) — Error Management. Table 14: Error Rate Error Events Capture RapidIO Error Description Registers Implementation Specific The Tsi576 Switch uses the implementation specific error to combine with other error events, so that they can be included within the Error Rate reporting function.
Page 135: Port-Write Notifications
6. Event Notification > Port-write Notifications Table 14: Error Rate Error Events (Continued) Capture RapidIO Error Description Registers Non-outstanding ackID Link_response received with an ackID that is not outstanding The status of this error is contained in the LR_ILL_ACKID bit in the “RapidIO Port x Error Detect CSR”...
Page 136: Destination Id
6. Event Notification > Port-write Notifications 6.6.1 Destination ID There is only one port-write destination ID programmed for the entire device; a port-write event that occurs at any RapidIO port is sent to the same destination ID. The specified destination ID must be mapped within the port’s lookup table.
Page 137: Servicing Port-Writes
6. Event Notification > Port-write Notifications Table 15 shows the port write packet data payload for error reporting. Table 15: Port Write Packet Data Payload — Error Reporting Data Payload Byte Offset Word 0 Word 1 “RapidIO Component Tag CSR” on page 261 “RapidIO Port x Error Detect CSR”...
Page 138: Port-Writes And Hot Insertion/Hot Extraction Notification
6. Event Notification > Interrupt Notifications 6.6.4 Port-writes and Hot Insertion/Hot Extraction Notification Port-write requests are used to support hot insertion/extraction notification. For more information, refer to Hot Insertion and Hot Extraction (see “Hot Insertion and Hot Extraction” on page 59).
Page 139: Figure 30: Rapidio Block Interrupt And Port Write Hierarchy
6. Event Notification > Interrupt Notifications Figure 30: RapidIO Block Interrupt and Port Write Hierarchy OUTB_DEPTH, bit[27] SP_INT_STATUS OUTB_DEPTH_EN, bit[27] SP_CTL_INDEP INB_DEPTH, bit[28] SP_INT_STATUS INB_DEPTH_EN, bit[28] SP_CTL_INDEP INB_RDR, bit[29] SP_INT_STATUS INB_RDR_EN, bit[29] SP_CTL_INDEP PW_DIS MAX_RETRY, bit[26] SP_INT_STATUS PW_REQ to Port-Write Arbiter MAX_RETRY_EN, bit[26] SP_CTL_INDEP ILL_TRANS_ERR, bit[24] SP_INT_STATUS ILL_TRANS_EN, bit[24] SP_CTL_INDEP...
Page 140: Int_B Signal
6. Event Notification > Interrupt Notifications 6.7.1 INT_b Signal At the top level of the interrupt hierarchy is the external interrupt signal INT_b. This active low signal is asserted when any fully enabled interrupt occurs. The INT_b signal remains asserted until all interrupts are cleared within the device.
Page 141: Table 16: Port X Error And Status Register Status
6. Event Notification > Interrupt Notifications For those port specific interrupt causes which are not visible in the “Global Interrupt Status Register” on page 390 register, the interrupt handler must access the port’s registers to determine the cause of an interrupt.
Page 142: Interrupt Notification And Port-Writes
6. Event Notification > Interrupt Notifications 6.7.3 Interrupt Notification and Port-writes In the Tsi576, all RapidIO ports can also generate port-write messages based on interrupt events. Because of this architecture, the RapidIO interrupt enables also control whether a port-write message is issued for each interrupt.
Page 143: I 2 C Interface
C Interface Topics discussed include the following: • “Overview” • “Protocol Overview” • “Block Diagram” • “Tsi576 as I C Master” • “Tsi576 as I C Slave” • “Mailboxes” • “SMBus Support” • “Boot Load Sequence” • “Error Handling” • “Interrupt Handling”...
Page 144 7. I C Interface > Overview — I C Interface: Master interface – Supports 7-bit device addressing – Supports 0, 1, or 2-byte peripheral addressing – Supports 0, 1, 2, 3, or 4-byte data transfers – Reverts to slave mode if arbitration is lost –...
Page 145: Protocol Overview
7. I C Interface > Protocol Overview • CBUS compatibility — Tsi576 does not provide the DLEN signal — Tsi576 does not respond as a CBUS device when addressed with the CBUS address. The Tsi576 will interpret the CBUS address like any other 7-bit address and compare it to its device address without consideration for any other meaning.
Page 146: Block Diagram
7. I C Interface > Block Diagram Block Diagram Figure 32 shows an overview of the I C Interface. The shaded area is the block logic. The master and slave interfaces mux between control of the I2C_SD and I2C_SCLK I/O buffers, and connect through the package to the buses on the board.
Page 147: Figure 31: I 2 C Block Diagram
7. I C Interface > Block Diagram Figure 31: I C Block Diagram External External External Pull-ups C Device C Device C Buses on Circuit Board I2C_SCLK I2C_SCLK I2C_SD I2C_SD MA SA SEL PClk Reset Power-up Resets SCL Out SCL En SDA Out SDA En SDA In...
Page 148: Figure 32: I 2 C Reference Diagram
7. I C Interface > Block Diagram Figure 32: I C Reference Diagram I2C_SDA Signals I2C_SCLK Start/Restart Bit or Ack/Nak Stop (P) C Bus S/R Bit Bit Bit Bit Bit Bit A/N Protocol Byte Byte Byte Byte C Write Data Protocol Slave Address Peripheral Address Data Written to Device...
Page 149: Tsi576 As I 2 C Master
7. I C Interface > Tsi576 as I C Master The start/restart and stop conditions delineate a transaction – a master issues a start to claim ownership of the bus and a stop to release ownership. A restart is a repeated start condition between the first start and the terminating stop, and is used by a master to start a new transaction without giving up bus ownership.
Page 150: Figure 33: Software-Initiated Master Transactions
7. I C Interface > Tsi576 as I C Master Figure 33: Software-initiated Master Transactions Write Transaction (WRITE=1) From DEV_ADDR From PADDR From I2C_MST_WDATA Slave Address Peripheral Address Data Written to Device 7 Bit SlvAdr+Wr(0) PerAdrMsb PerAdrLsb WriteData WriteData WriteData WriteData pa_size=2 pa_size>=1...
Page 151: Example Eeprom Read And Write
7. I C Interface > Tsi576 as I C Master The overall procedure is to configure the device through the “I C Master Configuration Register”, load the data to be written in the “I C Master Transmit Data Register” (only needed for write operations), then load the “I C Master Control Register”...
Page 152: Master Bus Arbitration
7. I C Interface > Tsi576 as I C Master 7.4.3 Master Bus Arbitration Because the Tsi576 can operate in a multi-master I C system, it arbitrates for the I C bus as required by the I C Specification. During the Start and Slave Address phase, any unexpected state on the bus causes the Tsi576 to back off, release the bus, and wait for a Stop before retrying the transaction.
Page 153: Master Data Transactions
7. I C Interface > Tsi576 as I C Slave 7.4.6 Master Data Transactions After the peripheral address phase, if any, 0 to 4 bytes of data are read or written, followed by the Stop condition. The number of bytes to be transferred is set in the SIZE field of the “I C Master Control Register”...
Page 154 7. I C Interface > Tsi576 as I C Slave At the completion of any slave transaction, either the SA_OK or SA_FAIL interrupt status is updated in “I C Interrupt Status Register”. An optional interrupt can be sent to the Interrupt Controller, if enabled in SA_OK or SA_FAIL of the “I C Interrupt Enable...
Page 155: Slave Clock Stretching
7. I C Interface > Tsi576 as I C Slave Figure 34: Transaction Protocols for Tsi576 as Slave Write Transaction Starting at New SLV_PA Matched to SLV_ADDR Peripheral Slave Address Data Written to Peripheral Space Address 7 Bit SlvAddr+Wr(0) SLV_PA WriteData WriteData WriteData A...
Page 156: Slave Device Addressing
7. I C Interface > Tsi576 as I C Slave 7.5.2 Slave Device Addressing The Tsi576 supports 7-bit device addressing. The device address of the Tsi576 is set in the SLV_ADDR field of the “I C Slave Configuration Register”. For the Tsi576 to respond to an external master, the slave address on the bus must match either the address in the SLV_ADDR field, or the SMBus alert response address (see “SMBus Alert Response Protocol...
Page 157: External I C Register Map
7. I C Interface > Tsi576 as I C Slave 7.5.4 External I C Register Map Table 17 lists the register map that is visible to external I C devices. The lowest peripheral address maps to the LSB of the register, while the highest peripheral address maps to the MSB of the register. The external master can set the peripheral address to any location in the 256-byte range.
Page 158: Slave Write Data Transactions
7. I C Interface > Tsi576 as I C Slave Table 17: Externally Visible I C Register Map (Continued) Tsi576 Peripheral Address Range Mapped Register Description 0x20–0x23 EXI2C_ACC_STAT Returns status information on accesses performed by external devices, on the incoming/outgoing mailboxes and on the state of the alert Read-Only response flag.
Page 159: Slave Read Data Transactions
7. I C Interface > Tsi576 as I C Slave 7.5.6 Slave Read Data Transactions An external master is not required to set the peripheral address as part of a read transaction, but can do so by first writing the peripheral address and then issuing a Restart before writing any data. If not set, the read data starts wherever the peripheral address pointer was left by the previous transaction.
Page 160: Slave Access Examples
7. I C Interface > Tsi576 as I C Slave 7.5.8 Slave Access Examples This section shows a slave internal register access by an external master. The following abbreviations are used: <S> Start condition <R> Restart condition <SLVA> The 7-bit Tsi576 slave address (that matches SLV_ADDR) <PA=#>...
Page 161 7. I C Interface > Tsi576 as I C Slave 3. External device does an Alert Response request. Because ALERT_FLAG is asserted, the alert response address is ACK’d and the Tsi576 slave address is returned. C Sequence: <S><0001100><W><A><RD=SLVA+0><N><P> Following the transaction, SLV_PA is 0x84 (unchanged from previous transaction) and interrupt status SA_OK asserts.
Page 162 7. I C Interface > Tsi576 as I C Slave 6. External device sets up “I2C_SCLK Low and Arbitration Timeout Register” address (0x354) in EXI2C_REG_WADDR, then writes three registers back-to-back with 0x11223344, 0x55667788, and 0x99AABBCC. Because of the register auto-increment, and because the PA auto-wraps from 0x07 to 0x04, the writes can be completed in a stream.
Page 163: Resetting The I 2 C Slave Interface
7. I C Interface > Mailboxes 8. External device writes “Externally Visible I C Internal Access Control Register” to disable internal register auto-incrementing. C Sequence: <S><SLVA><W><PA=0x24><A><WD=0xA0><A><P> Following the transaction, SLV_PA is 0x25, “Externally Visible I C Internal Access Control Register” is 0x000000A0, and interrupt status SA_OK asserts.
Page 164: Figure 35: I 2 C Mailbox Operation
7. I C Interface > Mailboxes In addition, flags in the “Externally Visible I C Slave Access Status Register” are accessible by an external host to examine the mailbox status. Figure 35 shows the use of I C mailboxes. Figure 35: I C Mailbox Operation INCOMING MAIL EXTERNAL...
Page 165: Incoming Mailbox
7. I C Interface > SMBus Support 7.6.1 Incoming Mailbox To send data to the processor/host, an external I C master writes data to the incoming mailbox register, EXI2C_MBOX_IN, through the Tsi576 slave interface. When the Stop condition is seen (indicating the external master is completed writing to the mailbox), the slave interface sets the IMB_FLAG in the “Externally Visible I C Slave Access Status...
Page 166: Unsupported Smbus Features
7. I C Interface > SMBus Support 7.7.1 Unsupported SMBus Features The Tsi576 does not support the following SMBus features: • Non-host response to external SMBus host protocols, except for Alert Response Protocol • Address Resolution Protocol (ARP) or any related commands •...
Page 167: Figure 36: Smbus Protocol Support
7. I C Interface > SMBus Support Figure 36: SMBus Protocol Support SMBus Quick Command with Write, PA_SIZE*=0, SIZE*=0, WRITE*=1 SlaveAdr SMBus Quick Command with Read, PA_SIZE=0, SIZE=0, WRITE=0 SlaveAdr SMBus Send Byte, PA_SIZE=1, SIZE=0, WRITE=1 SlaveAdr PA0=Data SMBus Receive Byte, PA_SIZE=0, SIZE=1, DORDER*=1, WRITE=0 SlaveAdr RD0=Data SMBus Write Byte, PA_SIZE=1, SIZE=1, DORDER=1, WRITE=1...
Page 168: Smbus Alert Response Protocol Support
7. I C Interface > Boot Load Sequence 7.7.3 SMBus Alert Response Protocol Support The Tsi576 supports the SMBus Alert Response Protocol as either master or slave. As a master, an external device can be polled using a master read operation. As a slave, the Tsi576 slave interface responds to the Alert Response Address with the Tsi576’s slave device address based on the value of ALERT_FLAG in the “Externally Visible I...
Page 169: Figure 38: Boot Load Sequence
7. I C Interface > Boot Load Sequence Figure 38: Boot Load Sequence Device detection Retry Up to 6 Times to Find EEPROM After 6 NACKs, goto Exit Boot Init and Device Detect Not Idle Hard Reset Idle Detect EEPROM Reset Wait for Bus Idle Boot Addr Idle...
Page 170: Idle Detect
7. I C Interface > Boot Load Sequence 7.8.1 Idle Detect Upon exit from reset, it is unknown if another master is active. The Idle Detect period determines if the I2C_SCLK signal remains high long enough (roughly 50 microseconds) that it is unlikely another master is active.
Page 171: Eeprom Device Detection
7. I C Interface > Boot Load Sequence 7.8.4 EEPROM Device Detection Once the bus is available, the Tsi576 tries to connect to the EEPROM. A START condition is generated followed by BOOT_ADDR from the “I C Boot Control Register”. The upper 5 bits of that field reset to 0b10100 and the lower 2 bits are sampled from the I2C_SA[1:0] pins on exit from hard reset.
Page 172: Chaining
7. I C Interface > Boot Load Sequence 7.8.6 Chaining The boot loader provides for booting from multiple EEPROMs, or from multiple sections within a single EEPROM (or any combination of both). This process is called chaining. Chaining is invoked during the boot load sequence when three conditions occur together: •...
Page 173: Table 18: Format For Boot Loadable Eeprom
7. I C Interface > Boot Load Sequence The register load data consists of 8-byte fields aligned to 8-byte peripheral address boundaries. The first 4 bytes are the internal register address and the second 4 bytes are the register data. Note that the address and data are ordered from MSB to LSB within increasing peripheral byte addresses.
Page 174: I2C Boot Time
7. I C Interface > Boot Load Sequence As a second example, the following shows an EEPROM configured to first load the I2C_MST_CFG register then chain to address 0x80 in the same EEPROM and load the I2C_MST_TDATA register. Note that the chain requires loading the I2C_BOOT_CNTRL register. The new peripheral address is 0x80 >>...
Page 175: Accelerating Boot Load
7. I C Interface > Boot Load Sequence If there are no other devices contending for bus access, a 1-byte peripheral address is used, no boot acceleration techniques are used, and no retries are necessary for device detect, then boot time can be estimated as follows: Boot_Time = 50 us idle detect time +...
Page 176: Error Handling
7. I C Interface > Error Handling Error Handling The Tsi576 handles a number of I C errors and reports them with status bits, as summarized in Table Table 21: I C Error Handling Interrupt Status Bit Error Cause Access Type Tsi576 Response (Events) Master Access Errors...
Page 177 7. I C Interface > Error Handling Table 21: I C Error Handling (Continued) Interrupt Status Bit Error Cause Access Type Tsi576 Response (Events) Programmed register Read operation Read returns 0x00 SA_OK address accesses a Write operation Write data discarded SA_OK non-existent internal register block...
Page 178: Interrupt Handling
7. I C Interface > Interrupt Handling 7.10 Interrupt Handling C interrupts are generated as shown in Figure 39. An I C event detected by the I C Interface sets a bit in the “I C Interrupt Status Register” to a 1 to assert the interrupt. This bit is then anded with the corresponding bit in the “I C Interrupt Enable Register”...
Page 179: Events Versus Interrupts
7. I C Interface > Events versus Interrupts 7.11 Events versus Interrupts Interrupts are generated by I C events. Figure 40 shows the design of the event and interrupt logic. A single interrupt status bit may be derived from one or more events. The event registers provide control over the individual events that in turn produce the interrupt status.
Page 180: Figure 40: I 2 C Event And Interrupt Logic
7. I C Interface > Events versus Interrupts Figure 40: I C Event and Interrupt Logic Read I2C_INT_STAT to CLEAR (after snapshot) Write 1 to bit N in I2C_EVENT to CLEAR Event Asserted by Logic SETS Bit N I2C_NEW_EVENT Write 1 to bit N in I2C_NEW_EVENT Bit N or to related bit in I2C_INT_SET to SET I2C_EVENT...
Page 181: Timeouts
7. I C Interface > Timeouts Table 22: I C Interrupt to Events Mapping (Continued) Interrupt Status Bit Events Related to Interrupt BL_OK (Boot Load OK) BLOK (Boot Load OK Event) SA_FAIL (Slave Access Failed) SCOL (Slave Collision Detect Event) STRTO (Slave Transaction Timeout Event) SBTTO (Slave Byte Timeout Event) SSCLTO (Slave I2C_SCLK Low Timeout Event)
Page 182 7. I C Interface > Timeouts • Arbitration timeout (see “I2C_SCLK Low and Arbitration Timeout Register”) – This timeout applies only to master transactions initiated by setting the START bit in the “I C Master Control Register”. Its purpose is to limit the length of time the master controller tries to gain ownership of the bus.
Page 183 7. I C Interface > Timeouts • Transaction timeout (see “I C Byte/Transaction Timeout Register”) – This timeout is disabled on reset. It detects a situation where a master is keeping the bus for an extended period of time, as measured from the Start to Stop condition.
Page 184: Figure 41: I 2 C Timeout Periods
7. I C Interface > Timeouts Figure 41 shows the relationship of the I C time-outs to I C operations. Figure 41: I C Timeout Periods SCL Low Timeout I2C_SCLK Master or Slave From SCL sampled low to SCL sampled high Any collision on bus loses arbitration Arbitration Timeout START...
Page 185: Bus Timing
7. I C Interface > Bus Timing 7.13 Bus Timing Figure 42 shows the relationship of the bus timing parameters to the generation of the I2C_SCLK and I2C_SD signals on the I C bus. These parameters are configured in the following registers: •...
Page 186: Figure 42: I 2 C Bus Timing Diagrams
7. I C Interface > Bus Timing Figure 42: I C Bus Timing Diagrams I2C_SD START/RESTART Condition Master Only I2C_SCLK Setup Hold I2C_SD STOP Condition Master Only I2C_SCLK Setup I2C_SD I2C_SD Data Bit or Ack/Nack Master or Slave I2C_SCLK Setup Hold Nominal Low Nominal High...
Page 187: Start/Restart Condition Setup And Hold
7. I C Interface > Bus Timing 7.13.1 Start/Restart Condition Setup and Hold The Start/Restart Condition is generated by a master. As shown in Figure 42, the Start Setup time defines the minimum period both the I2C_SD and I2C_SCLK signals must be seen high (1) before the I2C_SD signal is pulled low (0) to trigger the Start.
Page 188: I2C_Sclk Nominal And Minimum Periods
7. I C Interface > Bus Timing 7.13.4 I2C_SCLK Nominal and Minimum Periods These parameters are used by the Tsi576 as a master to generate the I2C_SCLK clock. The master must obey the minimum times to conform to the I C Specification, and must also attempt to regulate the overall I2C_SCLK frequency to a defined period.
Page 189: Performance
Performance This chapter is a detailed description of the packet switching performance characteristics of the Tsi576. It consists of the following general topics: • “Overview” on page 189 • “Performance Monitoring” on page 190 • “Configuring the Tsi576 for Performance Measurements” on page 194 •...
Page 190: Performance Monitoring
8. Performance > Performance Monitoring Figure 43 illustrates the path a packet flows through a Tsi576. For Tsi576 latency performance, packet reception time begins with the time the first bit of a packet is seen on the input pins. Packet transmission begins when the first bit of a packet has been transmitted on the output pins.
Page 191: Table 23: Performance Monitoring Parameters
8. Performance > Performance Monitoring Performance monitoring decisions can be made by system software in real-time. The system software can be programmed to routinely read the performance monitoring registers, analyze the traffic flow patterns, and re-route accordingly to avoid congestion. Each Serial RapidIO port in the device has a copy of the performance monitoring registers.
Page 192: Traffic Efficiency
8. Performance > Performance Monitoring The following sub-sections describe the use of these parameters for monitoring the performance of the serial RapidIO ports in Tsi576. 8.2.1 Traffic Efficiency To characterize the efficiency of system traffic, the following parameters are used: 1.
Page 193: Bottleneck Detection
8. Performance > Performance Monitoring 8.2.3 Bottleneck Detection Monitoring the queue depth of the inbound and outbound modules can detect bottleneck traffic in the RapidIO interfaces. It can also be used to determine the period of time that packets of a given priority and below cannot be accepted.
Page 194: Configuring The Tsi576 For Performance Measurements
8. Performance > Configuring the Tsi576 for Performance Measurements Configuring the Tsi576 for Performance Measurements Performance measurements for complex traffic patterns can be specified for two different configurations of performance settings. The first configuration is for lightly loaded systems, where the likelihood of resource contention is low. This is known as the ‘fair share’...
Page 195: Tsi576 Rapidio Transmission Scheduler Settings
8. Performance > Port-to-Port Performance Characteristics 8.3.3 Tsi576 RapidIO Transmission Scheduler Settings The First Come, First Served packet scheduling algorithm is used in fair share systems. In this algorithm, the oldest packet is transmitted. If this packet is retried, then the oldest, highest priority packet is transmitted.
Page 196: Packet Throughput Performance
8. Performance > Port-to-Port Performance Characteristics Table 24: 4x/1x Latency Numbers Under No Congestion Ingress and Egress Ingress and Egress Reference Clock Port Width Baud Rate Minimum Latency (ns) 156.25MHz 4x mode 3.125 128.8 1.25 212.8 1x mode 3.125 131.2 152.8 1.25 260.8...
Page 197: Multicast Performance
8. Performance > Port-to-Port Performance Characteristics 8.4.2.2 Many Ports-to-One Port Throughput Performance Under a non-congested, many ports-to-one port packet traffic scenario, when all of the total ingress line rates are the same as the egress line rate (for example, four 1x mode, 3.125 Gbaud ingress ports all going to one 4x mode, 3.125 Gbaud egress port), the ingress port and egress port will always maintain line rates.
Page 198: Congestion Detection And Management
8. Performance > Congestion Detection and Management Table 25: 4x/1x Multicast Latency Numbers Under No Congestion Ingress and Egress Ingress and Egress Reference Clock Port Width Baud Rate (Gbaud) Minimum Latency (ns) 156.25MHz 3.125 163.2 178.4 1.25 254.4 3.125 188.8 210.4 1.25 318.4...
Page 199: Figure 44: Congestion And Detection Flowchart
8. Performance > Congestion Detection and Management Figure 44: Congestion and Detection Flowchart Start Receive packet into egress queue Number of Increment packets in queue Congestion Counter >= by 1 Depth ? Congestion Period timer expire Increment Leak Rate timer expire Congestion Period Counter by 1 Decrement...
Page 200: Congestion Registers
8. Performance > Congestion Detection and Management 8.5.1 Congestion Registers The Tsi576 contains registers in every port that can be used for the detection and monitoring of ingress and egress queue levels. The registers and their descriptions are as follows: •...
Page 201 8. Performance > Congestion Detection and Management — Threshold (THRESH): This field sets the threshold of how many times the ISF can re-order packets before the INB_RDR bit in the RIO Port x Interrupt Status register is set. The receiver versions of the registers contain the same fields as the registers related to the transmitters however the receiver registers pertain to the ingress buffer queue status.
Page 202: Figure 45: Congestion Example
8. Performance > Congestion Detection and Management Figure 45: Congestion Example Packets in Egress Queue (DEPTH field set to 4) Packet Receipt Rate Congestion Period Counter tick Congestion Period Count value Congestion Counter value 9 10 Leak Rate Timer tick Interrupt OUTB_DEPTH (Congestion Threshold set to 8) The Packet Receipt Rate in the chart indicates how quickly packets can enter and leave the queue.
Page 203: Jtag Interface
JTAG Interface This chapter describes the main features of the JTAG interface. It includes the following information: • “Overview” on page 203 • “JTAG Device Identification Number” on page 204 • “JTAG Register Access Details” on page 204 Overview The JTAG interface in Tsi576 is fully compliant with IEEE 1149.6 Boundary Scan Testing of Advanced Digital Networks as well as IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture standards.
Page 204: Jtag Device Identification Number
9. JTAG Interface > JTAG Device Identification Number JTAG Device Identification Number The JTAG device ID number for the Tsi576 is 0x20572167. JTAG Register Access Details The Tsi576 has the capability to read and write registers through the JTAG interface. Prior to using the IEEE Register Access Command feature, the part must be reset by driving TRST_b low.
Page 205: Write Access To Registers From The Jtag Interface
9. JTAG Interface > JTAG Register Access Details 9.3.2 Write Access to Registers from the JTAG Interface The following steps are required in order to write to a register through the JTAG interface: 1. Move to the Tap controller “Shift-IR” state and program the instruction register with IRAC instruction by writing into Instruction Register bits [2:0] with 3’b101.
Page 206 9. JTAG Interface > JTAG Register Access Details Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 207: Clocks, Resets And Power-Up Options
Clocks, Resets and Power-up Options This chapter describes the clock and reset of the Tsi576. It includes the following information: • “Clocks” on page 207 • “Resets” on page 211 • “Power-up Options” on page 214 10.1 Clocks The Tsi576 has three input clocks (S_CLK_p/n, P_CLK and I2C_SCLK) that are used to produce the Tsi576’s internal clock domains.
Page 208: Clocking Architecture
10. Clocks, Resets and Power-up Options > Clocks 10.1.1 Clocking Architecture The Tsi576 device relies on the reference clock (S_CLK_p/n) to generate most clocks inside device. S_CLK_p/n is fed into each SerDes. On the receive side, each SerDes recovers clocks from the data stream.
Page 209: Serdes Clocks
10. Clocks, Resets and Power-up Options > Clocks 10.1.2 SerDes Clocks All SerDes in Tsi576 use the same external reference clock (S_CLK_p/n). Depending on the pin or register setup, the SerDes generates the appropriate clocks to serialize/deserialize the data as well as the clocks for the internal logic.
Page 210: Clock Domains
10. Clocks, Resets and Power-up Options > Clocks 10.1.4 Clock Domains The Tsi576 contains a number of clock domains that are generated from the two input reference clocks. These domains are detailed in Table 27. For more information about special line rate support see “Clocking”...
Page 211: Resets
10. Clocks, Resets and Power-up Options > Resets 10.2 Resets Internal logic is responsible for automatically sequencing the removal of reset in all internal blocks to meet their requirements; no additional software programming is required. 10.2.1 Device Reset The Tsi576 can be reset the following ways: 1.
Page 212 10. Clocks, Resets and Power-up Options > Resets Timing of HARD_RST_b The Tsi576 requires the following timing for the HARD_RST_b signal: • HARD_RST_b must be asserted for a minimum of 1 millisecond (ms). • Tsi576 comes out of reset within 1 ms after HARD_RST_b is de-asserted after assertion. —...
Page 213: Per-Port Reset
10. Clocks, Resets and Power-up Options > Resets SW_RST_b is the only method to determine that a reset request has been received and should be handled as an interrupt. Port-writes cannot be sent for notification of reset request reception. 10.2.2 Per-Port Reset In order to reset an individual RapidIO port it must be powered down and back up again using the following procedure:...
Page 214: Power-Up Options
10. Clocks, Resets and Power-up Options > Power-up Options To ensure predictable operation of the Tsi576, for power-up reset, HARD_RST_b and TRST_b must be asserted prior to operation. After power-up, the TAP controller can be reset at any time and this does not affect the Tsi576 operation.
Page 215: Table 28: Power-Up Options Signals
10. Clocks, Resets and Power-up Options > Power-up Options Table 28: Power-Up Options Signals Pin Name Description SP{n}_MODESEL Selects the serial port operating mode for ports 0 and 6 0 = Port 0 or 6 operating in 4x mode 1 = Ports n and n+1 operating in 1x mode Note: The MAC_MODE in the “SRIO MAC x Digital Loopback and Clock Selection Register”...
Page 216: Default Port Speed
10. Clocks, Resets and Power-up Options > Power-up Options Table 28: Power-Up Options Signals Pin Name Description I2C_MA C Multibyte Address When driven high, I C module expects multi-byte peripheral addressing; otherwise, when driven low, single-byte peripheral address is assumed. I2C_SA[1,0] C Slave Address pins.
Page 217: Signals
Signals This chapter describes the signals and pinout of the Tsi576. It includes the following information: • “Overview” on page 217 • “Endian Ordering” on page 218 • “Port Numbering” on page 218 • “Signal Groupings” on page 219 • “Pinlist and Ballmap”...
Page 218: Endian Ordering
11. Signals > Endian Ordering Table 29: Signal Types (Continued) Pin Type Definition Core Power Core supply Core Ground Ground for core logic I/O Power I/O supply No connect These signals must be left unconnected. 11.2 Endian Ordering This document follows the bit-numbering convention adopted by RapidIO Interconnect Specification (Revision 1.3), where [0:7] is used to represent an 8 bit bus with bit 0 as the most-significant bit.
Page 219: Signal Groupings
11. Signals > Signal Groupings Table 30: Tsi576 Port Numbering Port Number RapidIO Port Mode Note Serial Port 9 (SP9) Unavailable This port is un-initialized and the port registers must be treated as reserved. Writes to port registers can cause undefined behavior and is not recommended.
Page 220: Figure 49: Signal Groupings
11. Signals > Signal Groupings Figure 49: Signal Groupings SP0_T[A,B,C,D]_[p,n] SP0_R[A,B,C,D]_[p,n] Ports JTAG SP0_REXT 4x Mode: 0 TRST_b TRST_b 1x Mode: 0,1 SP0_MODESEL SP1_PWRDN I2C_SCLK I2C_SD I2C_DISABLE SP6_T[A,B,C,D]_[p,n] I2C_MA SP6_R[A,B,C,D]_[p,n] I2C_SEL Ports SP6_REXT 4x Mode: 6 I2C_SA[1,0] 1x Mode: 6,7 SP6_PWRDN SP7_PWRDN MCES...
Page 221: Table 31: Tsi576 Signal Descriptions
11. Signals > Signal Groupings Table 31 describes the Tsi576 signals Table 31: Tsi576 Signal Descriptions Pin Name Type Description Recommended Termination Signal Port Numbering PORT {n} where {n} = 0, 2, 4, 6, 10, 12 Serial Port Transmit SP{n}_TA_p O, SRIO Port n Lane A Differential Non-inverting Transmit No termination required.
Page 222 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination SP{n}_RA_n I, SRIO Port n Lane A Differential Inverting Receive Data DC blocking capacitor of 0.1uF input (4x node) in series Port n Lane A Differential Inverting Receive Data input (1x mode) SP{n}_RB_p I, SRIO...
Page 223 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination SP{n}_PWRDN I/O, Port n Transmit and Receive Power Down Control Pin must be tied off according to LVTTL, This signal controls the state of Port n and Port the required configuration.
Page 224 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Serial Port Speed Select SP_IO_SPEED[1] I/O, Serial Port Transmit and Receive operating Pin must be tied off according to LVTTL, frequency select, bit 1. When combined with the required configuration.
Page 225 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Serial Port Lane Ordering Select SP_RX_SWAP I, LVTTL, Configures the order of 4x receive lanes on serial No termination required. ports[0,6]. Internal pull-down can be used 0 = A, B, C, D for logic 0.
Page 226 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination S_CLK_p I, CML Differential reference clock at 156.25MHz. The AC coupling capacitor of 0.1uF clock is used as a reference clock for the SerDes required.
Page 227 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination I2C_SCLK I/O, OD, C input/output clock, up to 100 kHz. No termination required. Internal LVTTL, pull-up can be used for logic 1. If an EEPROM is present on the I C bus, this clock Pull up to VDD_IO through a signal must be connected to the clock input of the...
Page 228 11. Signals > Signal Groupings Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination I2C_SEL I, LVTTL, C Pin Select. No termination required. Internal pull-up can be used for logic 1. Together with the I2C_SA[1,0] pins, the Tsi576 determines the lower 2 bits of the 7-bit address of Pull up to VDD_IO through a the EEPROM address it boots from.
Page 229: Pinlist And Ballmap
11. Signals > Pinlist and Ballmap Table 31: Tsi576 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Power Supplies SP_AVDD Port n and n+1: 3.3V supply for bias generator Refer to decoupling circuitry. This is required to be a low-noise supply. recommendations in the Tsi576 Hardware Manual for more information...
Page 230 11. Signals > Pinlist and Ballmap Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 231: Serial Rapidio Registers
Serial RapidIO Registers This chapter describes the Tsi576 registers. The following topics are discussed: • “Overview” on page 231 • “Port Numbering” on page 233 • “Conventions” on page 234 • “Register Map” on page 235 • “RapidIO Logical Layer and Transport Layer Registers” on page 247 •...
Page 232: Reserved Register Addresses And Fields
12. Serial RapidIO Registers > Overview 12.1.1 Reserved Register Addresses and Fields Reserved register addresses should not be read or written. Reads to reserved register addresses return unspecified data. Writes to reserved register addresses can lead to unpredictable results. For the RapidIO Standard Registers (Section 12.5 to 12.7), the Reserved fields should always be written as 0.
Page 233: Port Numbering
12. Serial RapidIO Registers > Port Numbering 12.2 Port Numbering The following table shows the mapping between port numbers and the physical ports. These port numbers are used within the destination ID lookup tables for ingress RapidIO ports and in numerous register configuration fields.
Page 234: Conventions
12. Serial RapidIO Registers > Conventions Table 34: Tsi576 Port Numbering Port Number RapidIO Port Mode Note Serial Port 14 (SP14) Unavailable This port is un-initialized and the port registers must be treated as reserved. Writes to port registers can cause undefined behavior and is not recommended.
Page 235: Register Map
12. Serial RapidIO Registers > Register Map 12.4 Register Map Table 35 gives an overview of the Tsi576 register map. Table 35: Register map overview Register Group Start Address End Address “RapidIO Logical Layer and Transport Layer Registers” on page 247 0x00000 0x000FC “RapidIO Physical Layer Registers”...
Page 236: Table 36: Register Map
12. Serial RapidIO Registers > Register Map Table 36 shows the Tsi576 register map. Table 36: Register Map Offset Register Name RapidIO Logical Layer and Transport Layer Registers 00000 RIO_DEV_ID “RapidIO Device Identity CAR” on page 248 00004 RIO_DEV_INFO “RapidIO Device Information CAR” on page 249 00008 RIO_ASBLY_ID “RapidIO Assembly Identity CAR”...
Page 237 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 00100 RIO_SP_MB_HEAD “RapidIO 1x or 4x Switch Port Maintenance Block Header” on page 272 00104 - 0011C Reserved 00120 RIO_SW_LT_CTL “RapidIO Switch Port Link Timeout Control CSR” on page 273 00124 - 00138 Reserved 0013C...
Page 238 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 160 - 17C Serial Port 1 Same set of registers as Serial Port 0, offset 140 - 15C. 180 - 19C Serial Port 2 1A0 - 1BC Serial Port 3 1C0 - 1DC Serial Port 4...
Page 239 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 01020 - 01024 Reserved 01028 RIO_PW_DESTID “RapidIO Port-Write Target Device ID CSR” on page 295 0102C - 0103C Reserved Per Port Error Management Registers 01040 SP0_ERR_DET “RapidIO Port x Error Detect CSR”...
Page 240 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 01080 - 010BC Serial Port 1 Same set of registers as for SP0, offsets 0x01040 - 0x0107C. 010C0 - 010FC Serial Port 2 01100 - 0113C Serial Port 3 01140 - 0117C Serial Port 4...
Page 241 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 1007C - 102FC Reserved 10300, 10304, RIO_MC_ID{0..7} “RIO Multicast Write ID x” on page 245 10308, 1030C, 10310, 10314, 10318, 1031C 10320, 10324, RIO_MC_MASK{0..7} “RIO Multicast Write Mask x” on page 246 10328, 1032C, 10330, 10334, 10338, 1033C...
Page 242 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 13004 SP0_CTL_INDEP “RapidIO Port x Control Independent Register” on page 321 13008 Reserved 1300C SP0_SEND_MCS “RapidIO Port x Send Multicast-Event Control Symbol Register” on page 324 13010 SP0_LUT_PAR_ERR_INFO “RapidIO Port x LUT Parity Error Info CSR”...
Page 243 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 1308C Reserved 13090 SP0_RX_Q_D_THRESH “RapidIO Port x Receiver Input Queue Depth Threshold Register” on page 357 13094 SP0_RX_Q_STATUS “RapidIO Port x Receiver Input Queue Congestion Status Register” on page 359 13098 SP0_RX_Q_PERIOD...
Page 244 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 13800 - 138FC Serial Port 8 Tsi576 un-initialized All registers as for SP0, offsets 0x13000 - 0x130FC. 13900 - 139AC Serial Port 9 Tsi576 un-initialized Same set of registers as for SP0, offsets 0x13000 - 0x130AC.
Page 245 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name 1B008 SP0_ISF_WM “RapidIO Port x ISF Watermarks” on page 399 1B00C Reserved 1B010 SP0_WRR_0 “Port x Prefer Unicast and Multicast Packet Prio 0 Register” on page 400 1B014 SP0_WRR_1...
Page 246 12. Serial RapidIO Registers > Register Map Table 36: Register Map (Continued) Offset Register Name SerDes Per Lane Registers 1D000 - 1DFFC Documented in the I C Register Chapter 1E000-1E01C Reserved 1E020 SMAC{0,2,4,6}_PG_CTL_0 “SerDes Lane 0 Pattern Generator Control Register” on page 405 1E024-1E02C Reserved 1E030...
Page 247: Rapidio Logical Layer And Transport Layer Registers
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5 RapidIO Logical Layer and Transport Layer Registers Every processing element contains a set of capability registers (CARs) that allows another processing element to determine its capabilities through maintenance read operations. All registers are 32 bits wide and are organized and accessed in 32-bit quantities.
Page 248: Rapidio Device Identity Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.1 RapidIO Device Identity CAR This register identifies the device and vendor information for the Tsi576. Register name: RIO_DEV_ID Register offset: 00000 Reset value: 0x0578_000D Bits 00:7 DEV_ID 07:15 DEV_ID 16:23...
Page 249: Rapidio Device Information Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.2 RapidIO Device Information CAR The SILICON_REV and METAL_REV fields in this register identify the device. Register name: RIO_DEV_INFO Register offset: 00004 Reset value: 0x0000_0010 Bits 00:07 Reserved 08:15 Reserved 16:23...
Page 250: Rapidio Assembly Identity Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.3 RapidIO Assembly Identity CAR This register contains assembly identification information about the Tsi576. Register name: RIO_ASBLY_ID Register offset: 00008 Reset value: 0x0001_000D Bits 00:07 ASBLY_ID 08:15 ASBLY_ID 16:23 ASBLY_VEN_ID 24:31...
Page 251: Rapidio Assembly Information Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.4 RapidIO Assembly Information CAR This register contains additional information about the assembly. Register name: RIO_ASBLY_INFO Register offset: 0000C Reset value: 0x0000_0100 Bits 00:07 ASBLY_REV 08:15 ASBLY_REV 16:23 EXT_FEAT_PTR 24:31 EXT_FEAT_PTR...
Page 252: Rapidio Processing Element Features Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.5 RapidIO Processing Element Features CAR This register identifies the major functionality provided by the processing element. Register name: RIO_PE_FEAT Register offset: 00010 Reset value: 0x1000_051F Bits 00:07 BRDG PROC Reserved...
Page 253 12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers (Continued) Reset Bits Name Description Type Value Reserved System bringup register extension 0 = System bringup register extension is not supported 1 = System bringup register extension is supported 24:26 Reserved CTLS...
Page 254: Rapidio Switch Port Information Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.6 RapidIO Switch Port Information CAR This register defines the switching capabilities of a processing element. Register name: RIO_SW_PORT Register offset: 00014 Reset value: Undefined Bits 00:07 Reserved 08:15 Reserved 16:23...
Page 255: Rapidio Source Operation Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.7 RapidIO Source Operation CAR This register defines the set of RapidIO I/O logical operations that can be issued by the Tsi576. The device can generate I/O logical maintenance read and write requests if it is required to access CARs and CSRs in other processing elements.
Page 256 12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers (Continued) Reset Bits Name Description Type Value PORT_WR Port-write operation The RapidIO ports support port-write generation to report errors. 30:31 Reserved Implementation defined Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 257: Rapidio Switch Multicast Support Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.8 RapidIO Switch Multicast Support CAR This register identifies the multicast programming model supported by a switch. The Tsi576 does not support the simple programming model (for more information, see the “RapidIO Multicast Mask Configuration Register”...
Page 258: Rapidio Route Lut Size Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.9 RapidIO Route LUT Size CAR This register tells host software that the Tsi576 supports 512 destination IDs in its lookup table (LUT). When the LUT_512 bit in the “RapidIO Port x Mode CSR”...
Page 259: Rapidio Switch Multicast Information Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.10 RapidIO Switch Multicast Information CAR This RapidIO standard register gives information about the multicast programming model, the number of multicast destination IDs supported, and the number of multicast masks supported. Register name: RIO_SW_MC_INFO Register offset: 00038 Reset value: 0x0000_0008...
Page 260: Rapidio Host Base Device Id Lock Csr
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.11 RapidIO Host Base Device ID Lock CSR The host base device ID lock CSR contains the base device ID value for the processing element in the system that is responsible for initializing this processing element. The HOST_BASE_ID field is a write-once/reset field.
Page 261: Rapidio Component Tag Csr
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.12 RapidIO Component Tag CSR This register is written by software. It is used for labeling and identifying the port-write transactions to the host. Register name: RIO_COMP_TAG Register offset: 0006C Reset value: 0x0000_0000 Bits 00:07...
Page 262: Rapidio Route Configuration Destid Csr
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.13 RapidIO Route Configuration DestID CSR This register and “RapidIO Route Configuration Output Port CSR” on page 263 operate together to provide indirect read and write access to the destination ID lookup tables (LUTs). Writes to the LUTs through these registers affect the LUTs of all ports on the device.
Page 263: Rapidio Route Configuration Output Port Csr
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.14 RapidIO Route Configuration Output Port CSR This register and “RapidIO Route Configuration DestID CSR” on page 262 operate together to provide indirect read and write access to the LUTs. Writes to the LUTs through these registers affect the LUTs of all ports on the device.
Page 264: Rapidio Route Lut Attributes (Default Port) Csr
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.15 RapidIO Route LUT Attributes (Default Port) CSR This register provides a default route for packets that do not match a valid entry in the destination ID lookup table (LUT). By default, the default route is unmapped and packets that attempt to use the default route are discarded.
Page 265: Rapidio Multicast Mask Configuration Register
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.16 RapidIO Multicast Mask Configuration Register This register is used to add and remove egress port numbers to multicast masks. This can be completed either before or after a mask is bound to a destination ID and placed in the multicast group table. This register can also be used to retrieve the current configuration of a multimask mask.
Page 266 12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers (Continued) Reset Bits Name Description Type Value 25:27 MASK_CMD Specifies the mask action on a write. Contains the last value written for read operations. • 000 = Write_to_Verify. This write is only to set up a Multicast_Mask and Egress_Port_Number for a subsequent read of this register to check the Port_Present bit.
Page 267: Rapidio Multicast Destid Configuration Register
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.17 RapidIO Multicast DestID Configuration Register This register is used to configure the multicast group table. It contains the association between a destination ID and a multicast mask number. The association is formed or removed only when the “RapidIO Multicast DestID Association Register”...
Page 268: Rapidio Multicast Destid Association Register
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.18 RapidIO Multicast DestID Association Register This register populates and depopulates the multicast group table. When this register is written, the device consults the value in the “RapidIO Multicast DestID Configuration Register” on page 267 register to determine which destination ID is associated with which multicast mask (or which association must be removed).
Page 269 12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers (Continued) Reset Bits Name Description Type Value 25:26 Command • 00 = Verify Association This read checks the association status, for a given transport type, between a given destination ID and a multicast mask number.
Page 270: Rapidio Physical Layer Registers
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6 RapidIO Physical Layer Registers This section describes the Command and Status Register (CSR) set. All registers in the set are 32-bits long and aligned to a 32-bit boundary. These registers allow an external processing element to determine the capabilities, configuration, and status of a processing element using the Serial physical layer.
Page 271 12. Serial RapidIO Registers > RapidIO Physical Layer Registers Table 37: Physical Interface Register Offsets RapidIO Port x Registers Port Offset Description 0x0240 Tsi576 un-initialized 0x0260 Tsi576 un-initialized 0x0280 1x serial port 0x02A0 1x serial port 0x02C0 1x serial port 0x02E0 1x serial port 0x0300...
Page 272: Rapidio 1X Or 4X Switch Port Maintenance Block Header
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.1 RapidIO 1x or 4x Switch Port Maintenance Block Header This register contains the block header information. Register name: RIO_SW_MB_HEAD Register offset: 100 Reset value: 0x1000_0009 Bits 00:07 EF_PTR 08:15 EF_PTR 16:23 EF_ID 24:31...
Page 273: Rapidio Switch Port Link Timeout Control Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.2 RapidIO Switch Port Link Timeout Control CSR This register contains the timeout timer value for all ports on a device. This timeout is for link events such as sending a packet and receiving the corresponding acknowledge, or sending a link-request and receiving the corresponding link-response.
Page 274: Rapidio Switch Port General Control Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.3 RapidIO Switch Port General Control CSR This register applies to all ports on the device. A device has only one copy of the bits in this register. These bits are also accessible through the Port General Control CSR of any other physical layer implemented on a device.
Page 275: Rapidio Serial Port X Link Maintenance Request Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.4 RapidIO Serial Port x Link Maintenance Request CSR According to the RapidIO Interconnect Specification (Revision 1.3) only one link maintenance request can be outstanding at a time. However, the Tsi576 can be instructed to produce four consecutive link maintenance requests in order to quickly re-establish a link.
Page 276 12. Serial RapidIO Registers > RapidIO Physical Layer Registers Writing to this register on a port in normal operation affects traffic on that port. This register should only be used on ports in an error state. Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 277: Rapidio Serial Port X Link Maintenance Response Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.5 RapidIO Serial Port x Link Maintenance Response CSR This register is accessed by an external RapidIO device. A read of this register returns the status from the last link-response received from the link-partner due to a link-request/input-status issued using the RapidIO Serial Port x Link Maintenance Request CSR CSR or the RapidIO Port x Control Symbol Transmit register.
Page 278: Rapidio Serial Port X Local Ackid Status Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.6 RapidIO Serial Port x Local ackID Status CSR A read to this register returns the local ackID for both the inbound and outbound port of the device. Register name: SP{0..15}_ACKID_STAT Register offset: 148, 168, 188, 1A8, 1C8, 1E8, 208, 228, 248, 268, 288, 2A8, 2C8, 2E8, 308, 328 Reset value: 0x0000_0000...
Page 279 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value 27:31 OUTBOUND Outbound Acknowledge ID Next ackID to be transmitted by the port. Software can write this field to force re-transmission of outstanding unacknowledged packets, in order to manually implement error recovery.
Page 280: Rapidio Port X Error And Status Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.7 RapidIO Port x Error and Status CSR This register contains the port error and status information. This register returns 0x0000001 if it is read when the port is powered down. Register name: SP{0..15}_ERR_STATUS Register offset: 158, 178, 198, 1B8, 1D8, 1F8, 218, 238, 258, 278, 298, 2B8, 2D8, 2F8, 318, 338...
Page 281 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value OUTPUT_R Output Retried Outbound port has received a packet-retry control symbol and cannot make forward progress. This bit is set when the Output Retry-stopped bit (bit 13) is set. This bit is cleared after receiving a packet-accepted or packet-not-accepted control symbol.
Page 282 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value PORT_ERR Port Error R/W1C PORT_ERR on the even port is composed of a logical OR of PORT_ERR signal produced by the individual lanes independent of whether the MAC is configured in 4x mode or 1x mode.
Page 283: Rapidio Serial Port X Control Csr
12. Serial RapidIO Registers > RapidIO Physical Layer Registers 12.6.8 RapidIO Serial Port x Control CSR This register returns a default value when read in power down mode. This register returns 0x0000001 if it is read when the port is powered down. Register name: SP{0..15}_CTL Register offset: 15C, 17C, 19C, 1BC, 1DC, 1FC, 21C, 23C, 25C, 27C, 29C, 2BC, 2DC, 2FC, 31C, 33C...
Page 284 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value OVER_PWIDTH Override Port Width Software port configuration that overrides the hardware size. This field is valid only if the PORT_WIDTH field is set to 01 and the port is operating in 4x mode.
Page 285 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value ERR_DIS Error Checking Disable - physical layer CRC error only 0 = Enable error checking and recovery 1 = Disable error checking and recovery. Retransmission is suppressed for all packets.
Page 286 12. Serial RapidIO Registers > RapidIO Physical Layer Registers (Continued) Reset Bits Name Description Type Value PORT_LOCKOUT Port Lockout 0 = The packets that may be received and issued are controlled by the state of the Output Port Enable and Input Port Enable bits. 1= This port is stopped and is not enabled to issue or receive any packets.
Page 287: Rapidio Error Management Extension Registers
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7 RapidIO Error Management Extension Registers This section describes the registers in the Extended Features block (EF_ID = 0x0007), which is defined in Part VIII of the RapidIO specification. These registers enable an external processing element to manage the error status and reporting for a processing element.
Page 288: Port Behavior When Error Rate Failed Threshold Is Reached
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers Table 38: Error Management Registers (Continued) Port Offset Description 0x1280 Tsi576 un-initialized SP10 0x12C0 1x serial port SP11 0x1300 1x serial port SP12 0x1340 1x serial port SP13 0x1380 1x serial port SP14 0x13C0 Tsi576 un-initialized...
Page 289: Rapidio Error Reporting Block Header
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.2 RapidIO Error Reporting Block Header The error reporting block header indicates the start of the Error Management Extensions registers in the Tsi576. Register name: RIO_ERR_RPT_BH Register offset: 1000 Reset value: 0x0000_0007 Bits 00:07 EF_PTR...
Page 290: Rapidio Logical And Transport Layer Error Detect Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.3 RapidIO Logical and Transport Layer Error Detect CSR This register indicates the error that was detected by the Logical or Transport logic layer. Multiple bits can be set in the register if simultaneous errors are detected during the same clock cycle errors are logged.
Page 291: Rapidio Logical And Transport Layer Error Enable Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.4 RapidIO Logical and Transport Layer Error Enable CSR This register contains the bits that control if an error condition locks the Logical/Transport Layer Error Detect and Capture registers, and is reported to the system host through an interrupt and/or a port-write. For switches, the errors detected are limited to maintenance packets (maintenance requests, maintenance responses, and port writes) with a hop count of 0.
Page 292: Rapidio Logical And Transport Layer Address Capture Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.5 RapidIO Logical and Transport Layer Address Capture CSR This register contains error information. It is locked when a Logical/Transport error is detected and the corresponding enable bit is set. For switches, the errors detected are limited to maintenance packets (maintenance requests, maintenance responses, and port writes) with a hop count of 0.
Page 293: Rapidio Logical And Transport Layer Device Id Capture Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.6 RapidIO Logical and Transport Layer Device ID Capture CSR This register contains error information, specifically the device ID field values for failed transactions. It is locked when a Logical/Transport error is detected and the corresponding enable bit is set. When the TT field of the erroneous message is not a defined value, the contents of this register are bytes 3 and 4 of the packet received.
Page 294: Rapidio Logical And Transport Layer Control Capture Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.7 RapidIO Logical and Transport Layer Control Capture CSR This register contains error information, specifically the message type and subtype field values for failed transactions. It is locked when a Logical/Transport error is detected and the corresponding enable bit is set.
Page 295: Rapidio Port-Write Target Device Id Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.8 RapidIO Port-Write Target Device ID CSR This register contains the target device ID to be used when the switch generates a maintenance port-write operation to report errors to a system host. Port-write packets are routed to the output port defined by the routing LUT of the switch.
Page 296: Rapidio Port X Error Detect Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.9 RapidIO Port x Error Detect CSR This register indicates transmission errors that are detected by the hardware. Each write of a non-zero value to the Port x Error Detect CSR causes the Error Rate Counter to increment, if the corresponding error bit is enabled in the “RapidIO Port x Error Rate Enable CSR”...
Page 297 12. Serial RapidIO Registers > RapidIO Error Management Extension Registers Reset Bits Name Description Type Value IMP_SPEC_ERR Implementation Specific Error R/W0C Detected Logical/Transport error per port. This bit indicates one or more of the following illegal field errors: • Reserved transport type (TT) detected (TT field = 10 or 11 for all but maintenance packets with hop count = 0) •...
Page 298 12. Serial RapidIO Registers > RapidIO Error Management Extension Registers (Continued) Reset Bits Name Description Type Value LR_ACKID_ILL Link response received with an ackID that is not outstanding. R/W0C The Capture register does not have valid information during this error detection. During a recovery attempt by the Tsi576, it issued a link request control symbol to its link partner in order to attempt to clear the outstanding port error states.
Page 299: Rapidio Port X Error Rate Enable Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.10 RapidIO Port x Error Rate Enable CSR This register contains the bits that control when an error condition is allowed to increment the error rate counter. and be captured in the error capture register. Each write of a non-zero value to the “RapidIO Port x Error Detect CSR”...
Page 300 12. Serial RapidIO Registers > RapidIO Error Management Extension Registers (Continued) Reset Bits Name Description Type Value CS_NOT_ACC_ Enable error rate counting. Received packet-not-accepted control symbol. PKT_ILL_ACKID_ Enable error rate counting. Received packet with unexpected ackID. PKT_CRC_ERR_E Enable error rate counting. Received packet with a CRC error.
Page 301: Rapidio Port X Error Capture Attributes Csr And Debug 0
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.11 RapidIO Port x Error Capture Attributes CSR and Debug 0 This register indicates the type of information contained in the Port x Error Capture registers. In the case of multiple detected errors during the same clock cycle, only one of the errors must be reflected in the error type (ERR_TYPE) field.
Page 302 12. Serial RapidIO Registers > RapidIO Error Management Extension Registers Table 40: ERR_TYPE Values ERR_TYPE Value Name Error Description Valid Data Capture 00000 Bit 0 = IMP_SPEC_ERR Reserved Transport Type Max Retry Error Occurred Unmapped DestID Error Parity Error in Lookup Table ISF TEA Error Multicast TEA Error Port Error...
Page 303: Rapidio Port X Packet And Control Symbol Error Capture Csr 0 And Debug 1
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.12 RapidIO Port x Packet and Control Symbol Error Capture CSR 0 and Debug 1 In debug mode this register is unlocked. It contains bytes 4 to 7 of the debug packet being composed. During normal operation, this register captures bytes 0 to 3 of the packet, or the entire control symbol, that was detected to be in error.
Page 304: Rapidio Port X Packet Error Capture Csr 1 And Debug 2
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.13 RapidIO Port x Packet Error Capture CSR 1 and Debug 2 Register name: SP{0..15}_ERR_CAPT_1_DBG2 Register offset: 1050, 1090, 10D0, 1110, 1150, 1190, 11D0, 1210, 1250, 1290, 12D0, 1310, Reset value: 0x0000_0000 1350, 1390, 13D0, 1410 Bits 00:7...
Page 305: Rapidio Port X Packet Error Capture Csr 3 And Debug 4
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.15 RapidIO Port x Packet Error Capture CSR 3 and Debug 4 Register name: SP{0..15}_ERR_CAPT_3_DBG4 Register offset: 1058, 1098, 10D8, 1118, 1158, 1198, 11D8, 1218, 1258, 1298, 12D8, 1318, Reset value: 0x0000_0000 1358, 1398, 13D8, 1418 Bits CAPT_3[0:7]...
Page 306: Rapidio Port X Error Rate Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.16 RapidIO Port x Error Rate CSR This register and the “RapidIO Port x Error Rate Threshold CSR” on page 308 are used to monitor and control the reporting of transmission errors. Register name: SP{0..15}_ERR_RATE Register offset: 1068, 10A8, 10E8, 1128, 1168, 11A8, 11E8, 1228, 1268, 12A8, 12E8, 1328,...
Page 307 12. Serial RapidIO Registers > RapidIO Error Management Extension Registers (Continued) Reset Bits Name Description Type Value 24:31 ERR_ Error Rate Counter RATE_ These bits maintain a count of the number of transmission errors that have been detected by the port. This number is decremented by the Error Rate Bias function.
Page 308: Rapidio Port X Error Rate Threshold Csr
12. Serial RapidIO Registers > RapidIO Error Management Extension Registers 12.7.17 RapidIO Port x Error Rate Threshold CSR This register and the “RapidIO Port x Error Rate CSR” on page 306 are used to monitor and control the reporting of transmission errors. Register name: SP{0..15}_ERR_THRESH Register offset: 106C, 10AC, 10EC, 112C, 116C, 11AC, 11EC, 122C, 126C, 12AC, 12EC, 132C,...
Page 309: Idt-Specific Rapidio Registers
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8 IDT-Specific RapidIO Registers The registers in this section are specific to IDT’s switching products. The following table shows IDT-specific RapidIO Registers that are not defined in the RapidIO Interconnect Specification (Revision 1.3). When a individual port is powered down, the IDT-Specific RapidIO Registers are read only and return 0 with the exception of “RapidIO Port x Error and Status CSR”...
Page 310: Table 42: Tundra-Specific Per-Port Performance Registers
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers Table 41: Tundra-Specific Broadcast RapidIO Registers (Continued) Port Register Offset Description SP14 11E00 Tsi576 un-initialized SP15 11F00 Tsi576 un-initialized Non-Broadcast Per-Port Registers The following table shows the IDT-specific per-port registers not defined by the RapidIO Interconnect Specification (Revision 1.3).
Page 311: Rapidio Port X Discovery Timer
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.1 RapidIO Port x Discovery Timer This register defines discovery-timer value for the serial ports in 4x mode.. Register name: SP{BC,0..15}_DISCOVERY_TIMER Register offset: 10000, 11000, 11100, 11200, 11300, 11400, 11500, 11600, 11700, 11800, 11900, Reset value: 0x90C0_0000 11A00, 11B00, 11C00, 11D00, 11E00, 11F00 Bits...
Page 312: Rapidio Port X Mode Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.2 RapidIO Port x Mode CSR This register defines the mode of operation for the ports, and contains the interrupt enables for the Multicast-Event control symbol and Reset control symbol. Register name: SP{BC,0..15}_MODE Register offset: 10004, 11004, 11104, 11204, 11304, 11404, 11504, 11604, 11704, 11804, 11904, Reset value: 0x0300_0000...
Page 313 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value LUT_512 LUT_512 Sets the mode of the destination ID lookup table 0 = Global LUT (64K destination IDs, assigned with resolution of 256 destination IDs) 1 = One 512-entry local LUT 8:29 Reserved...
Page 314: Rapidio Port X Multicast-Event Control Symbol And Reset Control Symbol Interrupt Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.3 RapidIO Port x Multicast-Event Control Symbol and Reset Control Symbol Interrupt CSR This register contains the interrupt status for Multicast-Event control symbols and Reset control symbols. Register name: SP{BC,0..15}_CS_INT_STATUS Register offset: 10008, 11008, 11108, 11208, 11308, 11408, 11508, 11608, 11708, 11808, 11908, Reset value: 0x0000_0000 11A08, 11B08, 11C08, 11D08, 11E08, 11F08...
Page 315: Rapidio Port X Rapidio Watermarks
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.4 RapidIO Port x RapidIO Watermarks This register controls ingress buffer allocation for reception of packets for each port (see “Egress Watermark” on page 95). Register name: SP{BC,0..15}_RIO_WM Register offset: 1000C, 1100C, 1110C, 1120C, 1130C, 1140C, 1150C, 1160C, 1170C, 1180C, 1190C, Reset value: 0x0001_0203 11A0C, 11B0C, 11C0C, 11D0C, 11E0C, 11F0C...
Page 316: Rapidio Port X Route Config Destid Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.5 RapidIO Port x Route Config DestID CSR This register and SPx_ROUTE_CFG_PORT operate together to provide indirect read and write access to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and RIO_ROUTE_CFG_PORT, except the “RapidIO Port x Route Config Output Port CSR”...
Page 317: Rapidio Port X Route Config Output Port Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.6 RapidIO Port x Route Config Output Port CSR This register and SPx_ROUTE_CFG_DESTID operate together to provide indirect read and write access to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and RIO_ROUTE_CFG_PORT, except the RIO_ROUTE_CFG_PORT are per-port registers and they include an auto-increment bit to increment the contents of the destination ID register after a read or write operation.
Page 318: Rapidio Port X Local Routing Lut Base Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.7 RapidIO Port x Local Routing LUT Base CSR This register is required for switch devices that operate in a large system. For small systems, this register is ignored. The serial port supports local and global routing LUT pages. The number of entries is defined by the “RapidIO Route LUT Size CAR”...
Page 319: Rapidio Multicast Write Id X Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.8 RapidIO Multicast Write ID x Register This register contains the Multicast ID, which is associated to the multicast mask registers. The switch supports eight multicast groups and the Multicast ID registers for each multicast group must contain unique values.
Page 320: Rapidio Multicast Write Mask X Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.9 RapidIO Multicast Write Mask x Register This register contains the set of egress ports where a multicast packet is sent when it matches the destination ID associated with the mask. These bits form the multicast vector used by the broadcast buffer to determine which egress ports the packet is copied to.
Page 321: Rapidio Port X Control Independent Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.10 RapidIO Port x Control Independent Register This register is used for error recovery. Register name: SP{0..15}_CTL_INDEP Register offset: 13004, 13104, 13204, 13304, 13404, 13504, 13604, 13704, 13804, 13904, 13A04, Reset value: 0x0100_0000 13B04, 13C04, 13D04, 13E04, 13F04 Bits 00:07...
Page 322 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value DEBUG_MODE Mode of operation 0 = Normal 1 = Debug mode Debug mode unlocks the capture registers for writing and enables the debug packet generator feature. SEND_DBG_PKT Send Debug Packet 0 = Normal...
Page 323 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value IRQ_EN Interrupt Error Report Enable If enabled, the interrupt signal is high when the IRQ_ERR bit is set to MAX_RETRY_EN Maximum Retry Report Enable If enabled, the port-write and interrupt report an error when the MAX_RETRY_THRESHOLD is exceeded and the MAX_RETRY bit is set in the “RapidIO Port x Interrupt Status Register”...
Page 324: Rapidio Port X Send Multicast-Event Control Symbol Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.11 RapidIO Port x Send Multicast-Event Control Symbol Register When this register is written, it causes a Multicast-Event control symbol to be sent on the corresponding RapidIO output port. The port must be enabled for multicast control symbol forwarding through the MCS_EN bit in the SP{0..15}_CTL register.
Page 325: Rapidio Port X Lut Parity Error Info Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.12 RapidIO Port x LUT Parity Error Info CSR The RapidIO Port x LUT Parity Error Info CSR contains information about the look up operation that caused the parity error, as well as the LUT information associated with the parity error. The contents of this register are frozen when a LUT parity error is indicated in the “RapidIO Port x Interrupt Status Register”...
Page 326 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value LUT_VLD 0 = Indicates that the LUT entry is unmapped. The PORT_NUM field value should be 0xF in this case. 1 = Indicates the LUT entry is mapped. The PORT_NUM field value is the port to which the packet could be routed (0x0 to 0xF).
Page 327: Rapidio Port X Control Symbol Transmit
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.13 RapidIO Port x Control Symbol Transmit Writing to this register transmits a single control symbol to RapidIO. This register is only used for debug purposes. All control symbol fields are defined according to the RapidIO Interconnect Specification (Revision 1.3).
Page 328: Rapidio Port X Interrupt Status Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.14 RapidIO Port x Interrupt Status Register Register name: SP{0..15}_INT_STATUS Register offset: 13018, 13118, 13218, 13318, 13418, 13518, 13618, 13718, 13818, 13918, 13A18, Reset value: 0x0000_0000 13B18, 13C18, 13D18, 13E18, 13F18 Bits 00:07 Reserved 08:15...
Page 329 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value ILL_TRANS_ERR Illegal Transfer Error R/W1C This bit is set to 1 when the following occurs: • Received transaction has reserved tt field for all but maintenance packets with hop count = 0 •...
Page 330 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value INB_DEPTH Inbound Depth Interrupt R/W1C This value is set when Input Queue Depth Count reaches the maximum number defined in the Input Queue Depth Threshold field in “RapidIO Port x Receiver Input Queue Depth Threshold Register”...
Page 331: Rapidio Port X Interrupt Generate Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.15 RapidIO Port x Interrupt Generate Register This register can be used to generate the corresponding error in the “RapidIO Port x Interrupt Status Register” on page 328. When bits in the register are set, behavior associated with the error (port writes, interrupts) occur.
Page 332 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value INB_RDR_GEN Forces the INB_RDR bit to be set to 1. R/W1S This bit always reads as zero. Reserved Reserved R/W1S TEA_GEN Forces the TEA bit to be set to 1. R/W1S This bit always reads as zero.
Page 333: Idt-Specific Performance Registers
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9 IDT-Specific Performance Registers The registers in this section are specific to IDT’s switching products. The following table shows the IDT-specific per-port registers not defined by the RapidIO Interconnect Specification (Revision 1.3). It is not possible to broadcast to these registers.
Page 334: Rapidio Port X Performance Statistics Counter 0 And 1 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.1 RapidIO Port x Performance Statistics Counter 0 and 1 Control Register This register is used to control the performance statistics counters PS0 and PS1 registers. For every performance statistics register SPx_PSCy (where y refers to the Performance Statistics counter PS0 and PS1), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC0n1_CTRL register: •...
Page 335 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS0_PRIO2 Performance Stats Reg PS0 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 0 Register”...
Page 336 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS0_TYPE Performance Stats Reg PS0 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 0 Register”...
Page 337 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS1_PRIO0 Performance Stats Reg PS1 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 1 Register”...
Page 338: Rapidio Port X Performance Statistics Counter 2 And 3 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.2 RapidIO Port x Performance Statistics Counter 2 and 3 Control Register This register is used to control the performance statistics counters PS2 and PS3 registers. For every performance stats register SPx_PSCy (where y refers to the Performance Statistics counter PS2 and PS3), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC2n3_CTRL register: •...
Page 339 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS2_PRIO2 Performance Stats Reg PS2 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 4 and 5 Control Register”...
Page 340 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS2_TYPE Performance Stats Reg PS2 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 4 and 5 Control Register”...
Page 341 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS3_PRIO0 Performance Stats Reg PS3 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 3 Register”...
Page 342: Rapidio Port X Performance Statistics Counter 4 And 5 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.3 RapidIO Port x Performance Statistics Counter 4 and 5 Control Register This register is used to control the performance statistics counters PS4 and PS5 registers. For every performance stats register SPx_PSCy (where y refers to the Performance Statistics counter PS4 to PS5), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC4n5_CTRL register: •...
Page 343 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS4_PRIO2 Performance Stats Reg PS4 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 4 Register”...
Page 344 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS4_TYPE Performance Stats Reg PS4 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 4 Register”...
Page 345 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS5_PRIO0 Performance Stats Reg PS5 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x Performance Statistics Counter 5 Register”...
Page 346: Rapidio Port X Performance Statistics Counter 0 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.4 RapidIO Port x Performance Statistics Counter 0 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 347: Rapidio Port X Performance Statistics Counter 1 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.5 RapidIO Port x Performance Statistics Counter 1 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 348: Rapidio Port X Performance Statistics Counter 2 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.6 RapidIO Port x Performance Statistics Counter 2 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 349: Rapidio Port X Performance Statistics Counter 3 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.7 RapidIO Port x Performance Statistics Counter 3 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 350: Rapidio Port X Performance Statistics Counter 4 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.8 RapidIO Port x Performance Statistics Counter 4 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 351: Rapidio Port X Performance Statistics Counter 5 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.9 RapidIO Port x Performance Statistics Counter 5 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 352: Rapidio Port X Transmitter Output Queue Depth Threshold Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.10 RapidIO Port x Transmitter Output Queue Depth Threshold Register Queue depth registers are designed to allow for the rapid detection and notification of congestion. This register sets the Transmitter Queue Depth threshold, which is used in conjunction with “RapidIO Port x Transmitter Output Queue Congestion Status Register”...
Page 353 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:19 DEPTH This number is used to decide the congestion state of the output buffers. If the number of packets in the output queue meets or exceeds this number, the congestion counter is incremented.
Page 354: Rapidio Port X Transmitter Output Queue Congestion Status Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.11 RapidIO Port x Transmitter Output Queue Congestion Status Register This register is used to monitor data congestion in the output buffer. New packets accumulate in the output buffers, destined for the switching fabric. When the number of buffers in use equals or exceeds the threshold set in DEPTH field of the “RapidIO Port x Transmitter Output Queue Depth Threshold Register”, the CONG_CTR field in this register is incremented.
Page 355 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:31 CONG_THRESH Output Queue Depth Threshold 0x0000 If the CONG_CTR count is equal to the value in this field, an interrupt is reported to the system through the OUTB_DEPTH status bit in the “RapidIO Port x Interrupt Status Register”...
Page 356: Rapidio Port X Transmitter Output Queue Congestion Period Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.12 RapidIO Port x Transmitter Output Queue Congestion Period Register This register is used to monitor the duration of time that the output buffer is in congestion state. The CONG_PERIOD_CTR counter value is incremented for every N clock cycles specified by the CONG_PERIOD field in the “RapidIO Port x Transmitter Output Queue Depth Threshold Register”,...
Page 357: Rapidio Port X Receiver Input Queue Depth Threshold Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.13 RapidIO Port x Receiver Input Queue Depth Threshold Register Queue depth registers are designed to allow for the rapid detection and notification of congestion. This register sets the Receiver Queue Depth threshold, which is used in conjunction with “RapidIO Port x Receiver Input Queue Congestion Status Register”...
Page 358 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:19 DEPTH This number is used to decide the congestion state of the input buffers. If the number of packets in the input queue meets or exceeds this number, the congestion counter is incremented.
Page 359: Rapidio Port X Receiver Input Queue Congestion Status Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.14 RapidIO Port x Receiver Input Queue Congestion Status Register This register is used to monitor data congestion in the input buffer. New packets accumulate in the input buffers, destined for the switching fabric. When the number of buffers in use equals or exceeds the threshold set in DEPTH field of the “RapidIO Port x Receiver Input Queue Depth Threshold...
Page 360 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:31 CONG_THRESH Input Queue Depth Threshold 0x0000 If the CONG_CTR count is equal to the value in this field, an interrupt is reported to the system through the INB_DEPTH status bit in the “RapidIO Port x Interrupt Status Register”...
Page 361: Rapidio Port X Receiver Input Queue Congestion Period Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.15 RapidIO Port x Receiver Input Queue Congestion Period Register This register is used to monitor the duration of time that the input buffer is in congestion state. The CONG_PERIOD_CTR counter value is incremented for every N clock cycles specified by the CONG_PERIOD field in the “RapidIO Port x Receiver Input Queue Depth Threshold Register”, while...
Page 362: Rapidio Port X Reordering Counter Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.16 RapidIO Port x Reordering Counter Register When a packet cannot make forward progress due to internal switching congestion, the internal switching fabric selects packets in an order different from the order in which the packets were received. Each time this happens, it is counted as a “reorder”...
Page 363: Serial Port Electrical Layer Registers
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10 Serial Port Electrical Layer Registers The Serial Port Electrical Layer Registers are not defined in the RapidIO Interconnect Specification (Revision 1.3). They are specific to IDT’s switching products. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi576 performs a self-reset.
Page 364: Bypass_Init Functionality
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers The registers in the following table are accessible even when the serial RapidIO ports are in reset or powered down. Table 45: Serial Port Electrical Layer Registers Register Offset Description MAC0 130B0 Ports 0 and 1...
Page 365: Srio Mac X Serdes Configuration Channel 0
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.2 SRIO MAC x SerDes Configuration Channel 0 This register is used to control serial port SerDes channel 0. For more details on port configuration after power down, see “Port Power Down” on page Register name: SMAC{0,2,4,6,8,10,12,14}_CFG_CH0 Register offset: 130B0, 132B0, 134B0, 136B0, 138B0, 13AB0, 13CB0, 13EB0...
Page 366 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 12:15 TX_BOOST[ Transmit Boost control 3:0] Programmed boost value (ratio of drive level of transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)dB, except that setting tx_boost to 0 produces 0dB of boost.
Page 367 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value Reserved Note: Only write 1 to this reserved field. Integrated Device Technology Tsi576 User Manual www.idt.com June 6, 2016...
Page 368: Srio Mac X Serdes Configuration Channel 1
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.3 SRIO MAC x SerDes Configuration Channel 1 This register is used to control serial port SerDes channel 1. For more details on port configuration after power down, refer to “Port Power Down”...
Page 369 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 12:15 TX_BOOST[ Transmit Boost control. Programmed boost value (ratio of drive level of 3:0] transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)dB, except that setting tx_boost to 0 produces 0dB of boost.
Page 370: Srio Mac X Serdes Configuration Channel 2
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.4 SRIO MAC x SerDes Configuration Channel 2 This register is used to control serial port SerDes channel 2. For more details on port configuration after power down, refer to “Port Power Down”...
Page 371 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 12:15 TX_BOOST[3 Transmit Boost control. Programmed boost value (ratio of drive level of transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)dB, except that setting tx_boost to 0 produces 0dB of boost.
Page 372: Srio Mac X Serdes Configuration Channel 3
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.5 SRIO MAC x SerDes Configuration Channel 3 This register is used to control serial port SerDes channel 3. For more details on port configuration after power down, refer to “Port Power Down”...
Page 373 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 12:15 TX_BOOST[ Transmit Boost control. Programmed boost value (ratio of drive level of 3:0] transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)dB, except that setting tx_boost to 0 produces 0dB of boost.
Page 374: Srio Mac X Serdes Configuration Global
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.6 SRIO MAC x SerDes Configuration Global This register configures the SerDes of all four lanes of each port. Register name: SMAC{0,2,4,6,8,10,12,14}_CFG_GBL Register offset: 130C0, 132C0, 134C0, 136C0, 138C0, 13AC0, 13CC0, 13EC0 Reset value: undefined Bits 00:07...
Page 375: Table 46: Tx_Lvl Values
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 19:23 LOS_LVL[4:0 Control the LOS detection threshold. Level at which LOS is asserted falls between the programmed threshold + 2mV and programmed threshold + 55mV. Programmed threshold = ((LOS_LVL+1)/(32*16))*1.21 Vpk MPLL_PWR_ 0 = power down...
Page 376: Table 47: Ac Jtag Level Programmed By Acjt_Lvl[4:0]
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers Table 46: TX_LVL Values TX_LVL Value TX_LVL[0:4] Vdiff-pp (mV) 5'b01110 1065.4 5'b01111 1075.0 0x10 5'b10000 1084.7 0x11 5'b10001 1094.4 0x12 5'b10010 1104.1 0x13 5'b10011 1113.8 0x14 5'b10100 1123.5 0x15 5'b10101 1133.1 0x16 5'b10110...
Page 377 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers Table 47: AC JTAG level programmed by ACJT_LVL[4:0] Vmin level peak-to-peak Vmin level peak ACJT_LVL[4:0] differential (mV) single-ended (mV) 5’h07 5’h08 5’h09 5’h0A 5’h0B 5’h14 5’h15 5’h16 5’h17 5’h18 5’h19 5’h1A 5’h1B 1065...
Page 378: Srio Mac X Serdes Configuration Globalb
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.7 SRIO MAC x SerDes Configuration GlobalB This register configures the SerDes of all four ports. Register name: SMAC{0,2,4,6,8,10,12,14}_CFG_GBLB Register offset: 130C4, 132C4, 134C4, 136C4, 138C4, 13AC4, 13CC4, 13EC4 Reset value: 0x0023_014F Bits 00:07 Reserved...
Page 379: Srio Mac X Digital Loopback And Clock Selection Register
12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 12.10.8 SRIO MAC x Digital Loopback and Clock Selection Register This register consists of controls for Dead Link Timer and Digital Equipment Loopback (TX -> RX) as well as clock selection on a per port basis. Register name: Register offset:130C8, 132C8, 134C8, 136C8, SMAC{0,2,4,6,8,10,12,14}_DLOOP_CLK_SEL...
Page 380 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value 16:19 LINE_LB Line Loopback 0 = Disabled 1 = Enabled Line Loopback LINE_LB[3..0] = lane[D, C, B, A] Caution: This function is available but its use is not recommended as CDR and elastic buffering from receive to transmit is not available.
Page 381 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value SOFT_RST_ Software reset control for the even-numbered port. 0 = Normal mode of operation 1 = Even-numbered port held in reset Note: This bit only affects the port logic and per-port registers; it does not reset the SerDes.
Page 382: Internal Switching Fabric (Isf) Registers
12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers 12.11 Internal Switching Fabric (ISF) Registers These registers provide control and status information concerning time-out errors in data crossing the internal switching fabric. 12.11.1 Fabric Control Register The TEA signal is asserted when a timeout is detected on the ISF due to the requested destination being blocked.
Page 383 12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers Reset Bits Name Description Type Value 10:11 IN_ARB_M Input Arbitration Mode. This field selects the arbitration scheme used by the fabric’s ingress arbiters. 0 = First-come, first-served 1 = Strict Priority 1 2 = Reserved 3 = Strict Priority 2 12:13...
Page 384: Fabric Interrupt Status Register
12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers 12.11.2 Fabric Interrupt Status Register This register contains a status bit for every port on the fabric. The status bits indicate on which port(s) a Transaction Error Acknowledge (TEA) has occurred. Writing 1 to a bit clears it. The status bits are “ORed”...
Page 385 12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers (Continued) Reset Bits Name Description Type Value PORT5_IRQ Serial port 5 IRQ R/W1C PORT4_IRQ Serial port 4 IRQ R/W1C PORT3_IRQ Serial port 3 IRQ R/W1C PORT2_IRQ Serial port 2 IRQ R/W1C PORT1_IRQ Serial port 1 IRQ...
Page 386: Rapidio Broadcast Buffer Maximum Latency Expired Error Register
12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers 12.11.3 RapidIO Broadcast Buffer Maximum Latency Expired Error Register This register is a bit vector of ports which have had their maximum latency timer expire. If the AUTODEAD bit is set in the “RapidIO Multicast Maximum Latency Counter CSR”...
Page 387 12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers (Continued) Reset Bits Name Description Type Value P6_ERR Port 6 violated the maximum multicast latency time, and will not be R/W1C multicast to. P5_ERR Port 5 violated the maximum multicast latency time, and will not be R/W1C multicast to.
Page 388: Rapidio Broadcast Buffer Maximum Latency Expired Override
12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers 12.11.4 RapidIO Broadcast Buffer Maximum Latency Expired Override Writing to this register causes the corresponding bits in the “RapidIO Broadcast Buffer Maximum Latency Expired Error Register” on page 386 to be set. This bit causes the corresponding broadcast buffer to be purged of all data currently held in the broadcast buffer.
Page 389 12. Serial RapidIO Registers > Internal Switching Fabric (ISF) Registers (Continued) Reset Bits Name Description Type Value P7_SET Port 7 multicast mask is overridden once, every time this bit is written R/W1S as a 1. P6_SET Port 6 multicast mask is overridden once, every time this bit is written R/W1S as a 1.
Page 390: Utility Unit Registers
12. Serial RapidIO Registers > Utility Unit Registers 12.12 Utility Unit Registers The utility block contains global registers for interrupts and clocking. 12.12.1 Global Interrupt Status Register This register indicates which block within the Tsi576 has generated an interrupt. The interrupt requests from a given block are “ORed”...
Page 391 12. Serial RapidIO Registers > Utility Unit Registers (Continued) Reset Bits Name Description Type Value PORT12 Port 12 Interrupt PORT11 Port 11 Interrupt PORT10 Port 10 Interrupt PORT9 Port 9 Interrupt PORT8 Port 8 Interrupt PORT7 Port 7 Interrupt PORT6 Port 6 Interrupt PORT5 Port 5 Interrupt...
Page 392: Global Interrupt Enable Register
12. Serial RapidIO Registers > Utility Unit Registers 12.12.2 Global Interrupt Enable Register This register allows an internal interrupt request to signal an external interrupt through the INT_b pin. Register name: GLOB_INT_ENABLE Register offset: 1AC04 Reset value: 0x0000_0000 Bits 00:07 Reserved RCS_EN MCS_EN...
Page 393 12. Serial RapidIO Registers > Utility Unit Registers (Continued) Reset Bits Name Description Type Value PORT7_EN Port 7 Interrupt Enable PORT6_EN Port 6 Interrupt Enable PORT5_EN Port 5 Interrupt Enable PORT4_EN Port 4 Interrupt Enable PORT3_EN Port 3 Interrupt Enable PORT2_EN Port 2 Interrupt Enable PORT1_EN...
Page 394: Rapidio Port-Write Timeout Control Register
12. Serial RapidIO Registers > Utility Unit Registers 12.12.3 RapidIO Port-Write Timeout Control Register This register defines port-write time-out value. Whenever a port-write is pending, this timer begins counting. When this timer expires and the port write has not yet been cleared, another port-write is sent and the timer begins counting again.
Page 395: Rapidio Port Write Outstanding Request Register
12. Serial RapidIO Registers > Utility Unit Registers 12.12.4 RapidIO Port Write Outstanding Request Register This register displays the port number that has an outstanding port-write still in the port-write arbiter. After a port-write is sent, any remaining port-write requests from any port sets a bit in the register. Register name: RIO_PW_OREQ_STATUS Register offset: 1AC18 Reset value: 0x0000_0000...
Page 396: Mces Pin Control Register
12. Serial RapidIO Registers > Utility Unit Registers 12.12.5 MCES Pin Control Register This register controls the operation of the MCES pin. Register name: MCES_PIN_CTRL Register offset: 130D0 Reset value: 0x0000_0000 Bits 00:07 Reserved MCES_CTRL Reserved 08:15 Reserved 16:23 Reserved 24:31 Reserved Reset...
Page 397: Multicast Registers
12. Serial RapidIO Registers > Multicast Registers 12.13 Multicast Registers 12.13.1 RapidIO Multicast Register Version CSR This register identifies the multicast register interface version of the IDT specific registers that is supported by this device. Register name: RIO{0..15}_MC_REG_VER Register offset: 1B000,1B100, 1B200, 1B300, 1B400, 1B500, 1B600, 1B700, 1B800, 1B900, 1BA00, 1BB00, Reset value: 0x0000_0001 1BC00, 1BD00, 1BE00, 1BF00...
Page 398: Rapidio Multicast Maximum Latency Counter Csr
12. Serial RapidIO Registers > Multicast Registers 12.13.2 RapidIO Multicast Maximum Latency Counter CSR This register identifies the maximum time a packet copy can wait at the head of a broadcast buffer. If this time limit is exceeded the multicast packet and packet copies in flight to the broadcast buffer are dropped, and an interrupt is raised/port-write packet sent.
Page 399: Rapidio Port X Isf Watermarks
12. Serial RapidIO Registers > Multicast Registers 12.13.3 RapidIO Port x ISF Watermarks This register controls egress buffer allocation for reception of packets from ISF for each port. Register name: SP{0..15}_ISF_WM Register offset: 1B008,1B108, 1B208, 1B308, 1B408, 1B508, 1B608, 1B708, 1B808, 1B908, 1BA08, 1BB08, Reset value: 0x0001_0203 1BC08, 1BD08, 1BE08, 1BF08 Bits...
Page 400: Port X Prefer Unicast And Multicast Packet Prio 0 Register
12. Serial RapidIO Registers > Multicast Registers 12.13.4 Port x Prefer Unicast and Multicast Packet Prio 0 Register This register is used by the egress arbitration to control desired percentage of packets of either multicast or unicast within the same priority group. For more information, refer to “Arbitration for Egress Port”...
Page 401: Port X Prefer Unicast And Multicast Packet Prio 1 Register
12. Serial RapidIO Registers > Multicast Registers 12.13.5 Port x Prefer Unicast and Multicast Packet Prio 1 Register This register is used by the egress arbitration to control desired percentage of packets of either multicast or unicast within the same priority group. For more information, refer to “Arbitration for Egress Port”...
Page 402: Port X Prefer Unicast And Multicast Packet Prio 2 Register
12. Serial RapidIO Registers > Multicast Registers 12.13.6 Port x Prefer Unicast and Multicast Packet Prio 2 Register This register is used by the egress arbitration to control desired percentage of packets of either multicast or unicast within the same priority group. For more information, refer to “Arbitration for Egress Port”...
Page 403: Port X Prefer Unicast And Multicast Packet Prio 3 Register
12. Serial RapidIO Registers > Multicast Registers 12.13.7 Port x Prefer Unicast and Multicast Packet Prio 3 Register This register is used by the egress arbitration to control desired percentage of packets of either multicast or unicast within the same priority group. For more information, refer to “Arbitration for Egress Port”...
Page 404: Serdes Per Lane Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14 SerDes Per Lane Register This section details the access registers that control the functionality of the SerDes in Tsi576. The SerDes register offsets in this section are based on lane 0. In order to define lanes 1, 2, and 3 the offset is incremented by 0x40 for each lane.
Page 405: Serdes Lane 0 Pattern Generator Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.1 SerDes Lane 0 Pattern Generator Control Register This register controls the Pattern Generator in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PG_CTL_0 Register offset: 1E020, 1E220, 1E420, 1E620, 1E820, 1EA20, 1EC20, 1EE20 Reset value: 0x0000_0000 Bits 00:07 Reserved...
Page 406: Serdes Lane 1 Pattern Generator Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.2 SerDes Lane 1 Pattern Generator Control Register This register controls the Pattern Generator in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PG_CTL_1 Register offset: 1E060, 1E260, 1E460, 1E660, 1E860, 1EA60, 1EC60, 1EE60 Reset value: 0x0000_0000 Bits 00:07 Reserved...
Page 407: Serdes Lane 2 Pattern Generator Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.3 SerDes Lane 2 Pattern Generator Control Register This register controls the Pattern Generator in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PG_CTL_2 Register offset: 1E0A0, 1E2A0, 1E4A0, 1E6A0, 1E8A0, 1EAA0, 1ECA0, 1EEA0 Reset value: 0x0000_0000 Bits 00:07 Reserved...
Page 408: Serdes Lane 3 Pattern Generator Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.4 SerDes Lane 3 Pattern Generator Control Register This register controls the Pattern Generator in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PG_CTL_3 Register offset: 1E0E0, 1E2E0, 1E4E0, 1E6E0, 1E8E0, 1EAE0, 1ECE0, 1EEE0 Reset value: 0x0000_0000 Bits 00:07 Reserved...
Page 409: Serdes Lane 0 Pattern Matcher Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.5 SerDes Lane 0 Pattern Matcher Control Register This register contains the controls the Pattern Matcher and the error counters associated with the corresponding matcher in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PM_CTL_0 Register offset: 1E030, 1E230, 1E430, 1E630, 1E830, 1EA30, 1EC30, 1EE30 Reset value: 0x0000_0000...
Page 410: Serdes Lane 1 Pattern Matcher Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.6 SerDes Lane 1 Pattern Matcher Control Register This register contains the controls the Pattern Matcher and the error counters associated with the corresponding matcher in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PM_CTL_1 Register offset: 1E070, 1E270, 1E470, 1E670, 1E870, 1EA70, 1EC70, 1EE70 Reset value: 0x0000_0000...
Page 411: Serdes Lane 2 Pattern Matcher Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.7 SerDes Lane 2 Pattern Matcher Control Register This register contains the controls the Pattern Matcher and the error counters associated with the corresponding matcher in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PM_CTL_2 Register offset: 1E0B0, 1E2B0, 1E4B0, 1E6B0, 1E8B0, 1EAB0, 1ECB0, 1EEB0 Reset value: 0x0000_0000...
Page 412: Serdes Lane 3 Pattern Matcher Control Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.8 SerDes Lane 3 Pattern Matcher Control Register This register contains the controls the Pattern Matcher and the error counters associated with the corresponding matcher in each lane. Register name: SMAC{0,2,4,6,8,10,12,14}_PM_CTL_3 Register offset: 1E0F0, 1E2F0, 1E4F0, 1E6F0, 1E8F0, 1EAF0, 1ECF0, 1EEF0 Reset value: 0x0000_0000...
Page 413: Serdes Lane 0 Frequency And Phase Value Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.9 SerDes Lane 0 Frequency and Phase Value Register This register contains the frequency and phase of the incoming eyes on the SerDes. Register name: SMAC{0,2,4,6,8,10,12,14}_FP_VAL_0 Register offset: 1E034, 1E234, 1E434, 1E634, 1E834, 1EA34, 1EC34, 1EE34 Reset value: 0x0000_0000 Bits...
Page 414: Serdes Lane 1 Frequency And Phase Value Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.10 SerDes Lane 1 Frequency and Phase Value Register This register contains the frequency and phase of the incoming eyes on the SerDes. Register name: SMAC{0,2,4,6,8,10,12,14}_FP_VAL_1 Register offset: 1E074, 1E274, 1E474, 1E674, 1E874, 1EA74, 1EC74, 1EE74 Reset value: 0x0000_0000 Bits...
Page 415: Serdes Lane 2 Frequency And Phase Value Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.11 SerDes Lane 2 Frequency and Phase Value Register This register contains the frequency and phase of the incoming eyes on the SerDes. Register name: SMAC{0,2,4,6,8,10,12,14}_FP_VAL_2 Register offset: 1E0B4, 1E2B4, 1E4B4, 1E6B4, 1E8B4, 1EAB4, 1ECB4, 1EEB4 Reset value: 0x0000_0000 Bits...
Page 416: Serdes Lane 3 Frequency And Phase Value Register
12. Serial RapidIO Registers > SerDes Per Lane Register 12.14.12 SerDes Lane 3 Frequency and Phase Value Register This register contains the frequency and phase of the incoming eyes on the SerDes. Register name: SMAC{0,2,4,6,8,10,12,14}_FP_VAL_3 Register offset: 1E0F4, 1E2F4, 1E4F4, 1E6F4, 1E8F4, 1EAF4, 1ECF4, 1EEF4 Reset value: 0x0000_0000 Bits...
Page 417: I2C Registers
C Registers Topics discussed include the following: • “Register Map” • “Register Descriptions” 13.1 Register Map The following table lists the register map for the I C registers. All registers can be accessed through the internal register bus. A portion of the register space is visible to an external I C master through the slave interface.
Page 418 13. I2C Registers > Register Map Table 49: I C Register Map (Continued) Internal Peripheral Address Address Register Name 0x1D124 I2C_INT_SET “I C Interrupt Set Register” 0x1D12C I2C_SLV_CFG “I C Slave Configuration Register” 0x11D130– Reserved 0x1D13C 0x1D140 I2C_BOOT_CNTRL “I C Boot Control Register” 0x1D144–...
Page 419 13. I2C Registers > Register Map Table 49: I C Register Map (Continued) Internal Peripheral Address Address Register Name 0x1D308 I2C_NEW_EVENT “I C New Event Register” 0x1D30C I2C_EVENT_ENB “I C Enable Event Register” 0x1D310– Reserved 0x1D31C 0x1D320 I2C_DIVIDER “I C Time Period Divider Register” 0x1D324–...
Page 420: Register Descriptions
13. I2C Registers > Register Descriptions 13.2 Register Descriptions This section describes the I C registers. These registers are reset by a chip reset. 13.2.1 C Device ID Register This register identifies the version of the IDT I C block in this device. Register name: I2C_DEVID Register offset: 0x1D100 Reset value: 0x0000_0001...
Page 421: I 2 C Reset Register
13. I2C Registers > Register Descriptions 13.2.2 C Reset Register This register completes a reset of the I C block. This reset returns the logic to its idle, non-transacting state while retaining all configuration registers, such that the block does not have to be reprogrammed. This is provided for exceptional conditions.
Page 422: I 2 C Master Configuration Register
13. I2C Registers > Register Descriptions 13.2.3 C Master Configuration Register This register contains options that apply to master operations initiated through the “I C Master Control Register”. The configuration specifies the properties of the external slave device to which a read or write transaction will be directed.
Page 423 13. I2C Registers > Register Descriptions Do not change this register while a master operation is active. The effect on the transaction cannot be determined. Integrated Device Technology Tsi576 User Manual www.idt.com June 6, 2016...
Page 424: I 2 C Master Control Register
13. I2C Registers > Register Descriptions 13.2.4 C Master Control Register This register sets the peripheral address and to start an I C transaction. The transaction is directed to the device defined in the “I C Master Configuration Register”. Note: Software must not set the peripheral address and the SIZE parameters such that unintended page wrap-arounds occur in the target device.
Page 425 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 05:07 SIZE Number of bytes in an I C operation (read or write) 000 = 0 bytes 001 = 1 bytes 010 = 2 bytes 011 = 3 bytes 100 = 4 bytes 101 = Reserved (equivalent of 0 bytes) 110 = Reserved (equivalent of 0 bytes)
Page 426: Table 50: Master Operation Sequence
13. I2C Registers > Register Descriptions The following is the sequence triggered by setting the START bit: Table 50: Master Operation Sequence Phase Description Outcome 1. Begin transaction Start arbitration timer. 2. Address slave Detect bus idle. Any loss of arbitration repeats this phase. Phase completes with ACK.
Page 427: I 2 C Master Receive Data Register
13. I2C Registers > Register Descriptions 13.2.5 C Master Receive Data Register This register contains the data read from an external slave device following a read operation initiated using the “I C Master Control Register”. As bytes are read from the I C bus, they are placed in this register depending on DORDER in the “I Master Configuration...
Page 428: I 2 C Master Transmit Data Register
13. I2C Registers > Register Descriptions 13.2.6 C Master Transmit Data Register This register contains the data to be written (transmitted) to an external slave when a write operation is initiated using the “I C Master Control Register”. This register should be written with data to be sent prior to setting the START bit in that register.
Page 429: I 2 C Access Status Register
13. I2C Registers > Register Descriptions 13.2.7 C Access Status Register This register indicates the status of the I C block. Fields in this register change dynamically as operations are initiated or progress. Register name: I2C_ACC_STAT Register offset: 0x1D118 Reset value: 0x0000_0000 Bits 00:07 SLV_...
Page 430 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value SLV_WAIT Slave Wait 0 = Slave is not waiting for a STOP or RESTART 1 = Slave is waiting for a STOP or RESTART This bit is clear if the bus is not active or the slave address is being received or the slave is active.
Page 431 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 20:22 MST_ Master Phase PHASE 000 = START condition being sent 001 = External slave address being transmitted 010 = Peripheral address being transmitted 011 = RESTART condition being sent 100 = Data incoming (read operation) 101 = Data outgoing (write operation) 110 = STOP condition being sent...
Page 432: I 2 C Interrupt Status Register
13. I2C Registers > Register Descriptions 13.2.8 C Interrupt Status Register This register indicates the status of the I C interrupts. When an interrupt status bit is set, an interrupt is generated to the Interrupt Controller if the corresponding bit is enabled in the “I C Interrupt Enable Register”.
Page 433 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value BL_OK Boot Load OK R/W1C 0 = Interrupt status not asserted 1 = Boot load sequence completed successfully This will also be set if the boot loading was disabled at reset. 16:19 Reserved Reserved...
Page 434 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value MA_COL Master Collision R/W1C 0 = Interrupt status not asserted 1 = Collision (arbitration loss) occurred following the device address phase A transaction initiated using the “I C Master Control Register”...
Page 435: I 2 C Interrupt Enable Register
13. I2C Registers > Register Descriptions 13.2.9 C Interrupt Enable Register This register controls which of the interrupt status bits in the “I C Interrupt Status Register” will result in an interrupt asserted to the Interrupt Controller. It can only be accessed from the register bus. Register name: I2C_INT_ENABLE Register offset: 0x1D120 Reset value: 0x0000_0000...
Page 436 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value SA_WRITE Enable SA_WRITE Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled SA_READ Enable SA_READ Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled SA_OK Enable SA_OK Interrupt 0 = Interrupt is disabled...
Page 437: I 2 C Interrupt Set Register
13. I2C Registers > Register Descriptions 13.2.10 C Interrupt Set Register This register sets the status of the I C blocks interrupts. It can only be accessed from the register bus. Note: Setting an interrupt sets all related underlying events in the “I C New Event Register”.
Page 438 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value SA_WRITE Set SA_WRITE Interrupt R/W1S 0 = No effect 1 = Interrupt is set SA_READ Set SA_READ Interrupt R/W1S 0 = No effect 1 = Interrupt is set SA_OK Set SA_OK Interrupt R/W1S...
Page 439: I 2 C Slave Configuration Register
13. I2C Registers > Register Descriptions 13.2.11 C Slave Configuration Register This register configures the slave interface portion of the I C block. The slave interface is the logic that responds to transactions from an external master on the I C bus.
Page 440 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value ALRT_EN Alert Address Enable 0 = Do not respond to read of the Alert Response Address of 0001100 1 = Respond to read of the Alert Response Address of 0001100 if any bits are set in the “Externally Visible I Status Register”...
Page 441 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 25:31 SLV_ADDR Slave Address 0x30 This is the device address for the Tsi576 as an I C slave. An external master uses this address to access the Tsi576 peripheral register space.
Page 442: I 2 C Boot Control Register
13. I2C Registers > Register Descriptions 13.2.12 C Boot Control Register This register controls the boot load sequence that is initiated following a chip reset of the Tsi576. The initial boot load operation is controlled by the reset state of this register. Some of the fields are also latched from device pins at power-up.
Page 443 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value PSIZE Peripheral Address Size Undefined 0 = Use 1 byte for peripheral address 1 = Use 2 bytes for peripheral address This selects the number of bytes in the peripheral address. If 0 then only the least significant 5 bits of PADDR are used (+ 3 LSBs of 000).
Page 444 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 09:15 BOOT_ADDR Boot Device Address Undefined This is the device address that the Tsi576 will access during the boot load sequence. The least significant two bits [14:15] of this field are latched at power-up from the state of the I2C_SA[1:0] pins.
Page 445 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 19:31 PADDR Peripheral Address 0x0000 This is the most significant 5 or 13 bits of the peripheral address (depending on PSIZE setting). The least significant 3 bits are not programmable and are assumed 000; that is, the peripheral address must be aligned to a multiple of 8 address in the EEPROM.
Page 446: Externally Visible I C Internal Write Address Register
13. I2C Registers > Register Descriptions 13.2.13 Externally Visible I C Internal Write Address Register This register contains the internal register address set by an external I C master to be used for internal register writes when the “Externally Visible I C Internal Write Data Register”...
Page 447: Externally Visible I C Internal Write Data Register
13. I2C Registers > Register Descriptions 13.2.14 Externally Visible I C Internal Write Data Register This register contains the internal register data last written by an external I C master through the slave interface. The register is read-only from the register bus, and R/W from the I C bus through the slave interface.
Page 448: Externally Visible I C Internal Read Address Register
13. I2C Registers > Register Descriptions 13.2.15 Externally Visible I C Internal Read Address Register This register contains the internal register address set by an external I C master to be used for internal register reads when the “Externally Visible I C Internal Read Data Register”...
Page 449: Internal Read Data Register
13. I2C Registers > Register Descriptions 13.2.16 Externally Visible I C Internal Read Data Register This register contains the internal register data last read by an external I C master through the slave interface. The register is read-only from both the register bus and the I C bus through the slave interface.
Page 450: Slave Access Status Register
13. I2C Registers > Register Descriptions 13.2.17 Externally Visible I C Slave Access Status Register This register provides status indications to an external I C master. It is read-only from both the register bus and the I C bus through the slave interface. This register corresponds to the I C peripheral addresses 0x20 through 0x23.
Page 451 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value OMB_FLAG Outgoing Mailbox Flag 0 = Outgoing mailbox empty 1 = New data in the outgoing mailbox This bit is set when data is written to the outgoing mailbox register (“Externally Visible I C Outgoing Mailbox...
Page 452: Externally Visible I C Internal Access Control Register
13. I2C Registers > Register Descriptions 13.2.18 Externally Visible I C Internal Access Control Register This register allows an external I C master to configure the functionality for internal register accesses through the slave interface. This register is read-only from the register bus and R/W from the I C bus through the slave interface.
Page 453 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value 26:27 WSIZE Internal Register Write Access Size 00 = 1 byte (Reserved) 01 = 2 bytes 10 = 4 bytes – An internal register write is invoked once for each internal register, writing all 4 bytes from the “Externally Visible I...
Page 454: Status Register
13. I2C Registers > Register Descriptions 13.2.19 Externally Visible I C Status Register This register provides a summary view of status of the Tsi576. It can be polled by an external system management device. Any bit masked by its related enable, changing from 0 to 1, will cause ALERT_FLAG to be set in the “Externally Visible I C Slave Access Status...
Page 455 13. I2C Registers > Register Descriptions (Continued) Bits Name Description Type Reset Value SW_STAT2 Software Status Bit 2 0 = Status value 0 1 = Status value 1 This bit can be set or cleared by software using a register write for any system specific purpose.
Page 456 13. I2C Registers > Register Descriptions (Continued) Bits Name Description Type Reset Value Multicast Event Control Symbol Status 0 = No status asserted 1 = Status asserted Combined multicast event control system interrupt status from all ports. 10:12 Reserved Reserved LOGICAL Logical/Transport Layer Error 0 = No error...
Page 457 13. I2C Registers > Register Descriptions (Continued) Bits Name Description Type Reset Value PORT9 Port 9 Interrupt 0 = No interrupt 1 = Port 9 has asserted an interrupt to the processor PORT8 Port 8 Interrupt 0 = No interrupt 1 = Port 8 has asserted an interrupt to the processor PORT7 Port 7 Interrupt...
Page 458: Enable Register
13. I2C Registers > Register Descriptions 13.2.20 Externally Visible I C Enable Register Any bit set in this register will enable the equivalent bit in the “Externally Visible I C Status Register” to set the ALERT_FLAG. These enables do not affect whether events are set in the global status register, only whether the asserted events are allowed to set the ALERT_FLAG when changing from 0 to 1.
Page 459 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value IMBR Enable Incoming Mailbox Read 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Enable I C Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Enable TEA Alert Response...
Page 460 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value PORT12 Enable PORT12 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG PORT11 Enable PORT11 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG PORT10...
Page 461 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value PORT1 Enable PORT1 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG PORT0 Enable PORT0 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Integrated Device Technology...
Page 462: Externally Visible I C Outgoing Mailbox Register
13. I2C Registers > Register Descriptions 13.2.21 Externally Visible I C Outgoing Mailbox Register This register is the outgoing mailbox, allowing the processor to communicate data to an external I master. The register is R/W from the register bus, and read-only from the I C bus through the slave interface.
Page 463: Externally Visible I C Incoming Mailbox Register
13. I2C Registers > Register Descriptions 13.2.22 Externally Visible I C Incoming Mailbox Register This register is the incoming mailbox, allowing an external I C master to communicate data to the host processor. The register is read-only from the register bus, and R/W from the I C bus through the slave interface.
Page 464: I 2 C Event And Event Snapshot Registers
13. I2C Registers > Register Descriptions 13.2.23 C Event and Event Snapshot Registers These registers indicate events that occur within the I C block. For the I2C_EVENT register, each bit is an “or” of the corresponding bit in the “I C New Event Register”...
Page 465 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value Reserved Reserved DTIMER Diagnostic Timer Expired Event R/W1C 0 = Event not asserted 1 = Diagnostic timer has expired This event does not assert during the boot load sequence. The BLTO will assert instead.
Page 466 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value SSCLTO Slave I2C_SCLK Low Timeout Event R/W1C 0 = Event not asserted 1 = I2C_SCLK low timer expired during a slave transaction initiated by an external master 15:16 Reserved Reserved...
Page 467 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value BLOK Boot Load OK Event R/W1C 0 = Event not asserted 1 = The boot load sequence completed with no detectable errors. This bit is also asserted if boot load is disabled upon power up.
Page 468: I 2 C New Event Register
13. I2C Registers > Register Descriptions 13.2.24 C New Event Register This register indicates events that occurred since the last snapshot. This register is write-one-to-set. Writing a 1 to a bit position will set the event for diagnostic purposes. The register is cleared by writing to the I2C_EVENT register (see “I C Event and Event Snapshot...
Page 469 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value DCMDD Diagnostic Command Done Event R/W1S 0 = Event not asserted 1 = Event asserted IMBW Incoming Mailbox Write Event R/W1S 0 = Event not asserted 1 = Event asserted OMBR Outgoing Mailbox Read Event R/W1S...
Page 470 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value BLSZ Boot Load Size Error Event R/W1S 0 = Event not asserted 1 = Event asserted BLNOD Boot Load No Device Event R/W1S 0 = Event not asserted 1 = Event asserted BLOK Boot Load OK Event...
Page 471: I 2 C Enable Event Register
13. I2C Registers > Register Descriptions 13.2.25 C Enable Event Register This register modifies the function of the I2C_EVENT register (see “I C Event and Event Snapshot Registers”). Each bit in this register enables (1) or disables (0) the corresponding event in the I2C_EVENT register from asserting in the “I C Interrupt Status...
Page 472 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value IMBW Incoming Mailbox Write Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status OMBR Outgoing Mailbox Read Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status Reserved...
Page 473 13. I2C Registers > Register Descriptions (Continued) Reset Bits Name Description Type Value BLNOD Boot Load No Device Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status BLOK Boot Load OK Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status 24:25...
Page 474: I 2 C Time Period Divider Register
13. I2C Registers > Register Descriptions 13.2.26 C Time Period Divider Register This register provides programmable extension of the reference clock period into longer periods used by the timeout and idle detect timers. Register name: I2C_DIVIDER Register offset: 0x1D320 Reset value: 0x0063_03E7 Bits 00:07 Reserved...
Page 475: I 2 C Start Condition Setup/Hold Timing Register
13. I2C Registers > Register Descriptions 13.2.27 C Start Condition Setup/Hold Timing Register This register programs the setup and hold timing for the Start condition when generated by the master control logic. The timer periods are relative to the reference clock. This register is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM.
Page 476: I 2 C Stop/Idle Timing Register
13. I2C Registers > Register Descriptions 13.2.28 C Stop/Idle Timing Register This register programs the setup timing for the Stop condition when generated by the master control logic, and the Idle Detect timer. The Start Setup time doubles as the Stop Hold. The timer period for the Stop setup is relative to the reference clock.
Page 477: I2C_Sd Setup And Hold Timing Register
13. I2C Registers > Register Descriptions 13.2.29 I2C_SD Setup and Hold Timing Register This register programs the setup and hold times for the I2C_SD signal when output by either the master or slave interface. It is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM.
Page 478: I2C_Sclk High And Low Timing Register
13. I2C Registers > Register Descriptions 13.2.30 I2C_SCLK High and Low Timing Register This register programs the nominal high and low periods of the I2C_SCLK signal when generated by the master interface. It is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM.
Page 479: I2C_Sclk Minimum High And Low Timing Register
13. I2C Registers > Register Descriptions 13.2.31 I2C_SCLK Minimum High and Low Timing Register This register programs the minimum high and low periods of the I2C_SCLK signal when generated by the master interface. It is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM.
Page 480: I2C_Sclk Low And Arbitration Timeout Register
13. I2C Registers > Register Descriptions 13.2.32 I2C_SCLK Low and Arbitration Timeout Register This register programs the I2C_SCLK low timeout and the Arbitration timeout. The arbitration timer period is relative to the MSDIV period, and the I2C_SCLK low timeout period is relative to the USDIV period.
Page 481: I 2 C Byte/Transaction Timeout Register
13. I2C Registers > Register Descriptions 13.2.33 C Byte/Transaction Timeout Register This register programs the Transaction and Byte timeouts. The timer periods are relative to the USDIV period for the byte timeout, and relative to the MSDIV period for the transaction timeout. Register name: I2C_BYTE_TRAN_TIMEOUT Register offset: 0x1D358 Reset value: 0x0000_0000...
Page 482: I 2 C Boot And Diagnostic Timer
13. I2C Registers > Register Descriptions 13.2.34 C Boot and Diagnostic Timer This register programs a timer that times out the boot load sequence, and can be used after boot load as a general purpose timer. Register name: I2C_BOOT_DIAG_TIMER Register offset: 0x1D35C Reset value: 0x0000_0FA0 Bits 00:07...
Page 483: I 2 C Boot Load Diagnostic Progress Register
13. I2C Registers > Register Descriptions 13.2.35 C Boot Load Diagnostic Progress Register This register provides visibility of the register count and peripheral address during the boot load sequence. Register name: I2C_BOOT_DIAG_PROGRESS Register offset: 0x1D3B8 Reset value: 0x0000_0000 Bits 00:07 REGCNT 08:15 REGCNT...
Page 484: I 2 C Boot Load Diagnostic Configuration Register
13. I2C Registers > Register Descriptions 13.2.36 C Boot Load Diagnostic Configuration Register This register provides visibility of boot sequence information. Register name: I2C_BOOT_DIAG_CFG Register offset: 0x1D3BC Reset value: Undefined Bits 00:07 BOOTING BDIS PASIZE PINC Reserved 08:15 Reserved 16:23 Reserved 24:31 Reserved...
Page 485: Serial Rapidio Protocol Overview
Serial RapidIO Protocol Overview The RapidIO Physical Layer 1x/4x LP-Serial Specification addresses the physical layer requirements for devices utilizing an electrical serial connection medium. This specification defines a full duplex serial physical layer interface (link) between devices using unidirectional differential signals in each direction.
Page 486: Control Symbols
A. Serial RapidIO Protocol Overview > Physical Layer A.2.1 Control Symbols Two classes of control symbols are defined (stype0 and stype1) and are used for packet acknowledgment, link utility functions, link maintenance, and packet delineation. A control symbol is a 24-bit entity (including a 5-bit CRC code). The control symbol is used for packet delineation by placement at the beginning of a packet.
Page 487: Table 51: Special Characters And Encoding
A. Serial RapidIO Protocol Overview > Physical Layer Table 51 illustrates the Special Characters and their function as it applies to the serial protocol. Table 51: Special Characters and Encoding Number of Code Group Groups Encoding 8-bit Value /PD/ packet delimiter /K28.3/ 0x7C /SC/...
Page 488: Table 52: Control Symbol Construction
A. Serial RapidIO Protocol Overview > Physical Layer Table 52 illustrates the control symbol construction in 8-bit values. Further detail on the usage of the control symbols may be found in Part VI Physical Layer 1x/4x LP-Serial RapidIO Specification”. Table 52: Control Symbol Construction 3-bits 5-bits 5-bits...
Page 489 A. Serial RapidIO Protocol Overview > Physical Layer Table 52: Control Symbol Construction 3-bits 5-bits 5-bits 3-bits 3-bits 5-bits link response definition port_status [0-4] 00000 reserved 00001 reserved 00010 unrecoverable error unable to accept pkts 00011 reserved 00100 retry-stopped state 00101 error-stopped state 00110-011...
Page 490 A. Serial RapidIO Protocol Overview > Physical Layer Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 491: Clocking
Clocking This appendix describes device behavior outside the RapidIO Interconnect Specification (Revision 1.3) recommended operating line rates and clock frequencies. The following topics are discussed: • “Line Rate Support” on page 491 • “P_CLK Programming” on page 495 Line Rate Support The Tsi576 supports all of the RapidIO Interconnect Specification (Revision 1.3) specified line rates of 1.25, 2.50, and 3.125 Gbaud.
Page 492: Register Requirements Using 125 Mhz S_Clk For A 3.125 Gbps Link Rate
B. Clocking > Line Rate Support Table 53: Tsi576 Supported Line Rates (Continued) SP_IO_SPEED[1,0] Bit S_CLK_p/n (MHz) Baud Rate (Gbaud) Settings Register Settings 125.00 1.2500 Standard RapidIO Line Rate 125.00 2.5000 Standard RapidIO Line Rate 125.00 3.1250 “Register Requirements Using 125 MHz S_CLK for a Standard RapidIO Line Rate 3.125 Gbps Link Rate”...
Page 493 B. Clocking > Line Rate Support Using the Script The example EEPROM loading script in the “EEPROM Scripts” appendix of the Tsi576 User Manual configures ports six and eight of the Tsi576. Other ports can be added to the script and configured by editing the text.
Page 494 B. Clocking > Line Rate Support — Write offset 0x132B8 with 0x200C2513 — Write offset 0x132BC with 0x200C2513 6. Clear the MPLL_PWRON bit in the SMACx_CFG_GLOBAL register — Write offset 0x132c0 with 0xCA060004 — Ensure that BYPASS_INIT remains asserted 7. Set the MPLL_CK_OFF bit in the SMACx_CFG_GLOBAL register —...
Page 495: P_Clk Programming
B. Clocking > P_CLK Programming 15. Release the MAC from reset — Write offset 0x132c8 with 0x7FFF0002 P_CLK Programming The Tsi576 recommends a P_CLK operating frequency of 100 MHz. However, the device also supports P_CLK frequencies less than the recommended 100 MHz. The ability to support other P_CLK frequencies gives the Tsi576 flexibility in both application support and design.
Page 496: Table 54: Timer Values With P_Clk And Tval Variations
B. Clocking > P_CLK Programming Effects of changing the P_CLK frequency and TVAL setting can be seen in Table Table 54: Timer Values with P_CLK and TVAL Variations P_CLK Setting TVAL Setting Equation Timer Value 25 MHz 2,343,750 (0x23C346) 32/25 x 2,343,750 3 seconds 25 MHz 4,687,500 (0x47868C)
Page 497: Table 55: Timer Values With Discovery_Timer And P_Clk Variations
B. Clocking > P_CLK Programming DISCOVERY_TIMER_DONE The RapidIO Interconnect Specification (Revision 1.3) defines the DISCOVERY_TIMER_DONE as follows: Asserted when DISCOVERY_TIMER_EN has been continuously asserted for 12 +/- 4msec and the state machine is in the DISCOVERY state. The assertion of DISCOVERY_TIMER_DONE causes DISCOVERY_TIMER_EN to be de-asserted.
Page 498: Idt Specific Timers
B. Clocking > P_CLK Programming B.2.2 IDT Specific Timers The following sections describe how changing the P_CLK frequency to below the recommended 100 MHz operation affect the IDT-specific counters and state machines in the Tsi576. B.2.2.1 Dead Link Timer The Dead Link Timer period is controlled by the DLT_THRESH field in the SRIO MAC x Digital Loopback and Clock Selection Register.
Page 499: I 2 C Interface And Timers
B. Clocking > P_CLK Programming B.2.3 C interface and Timers The I C interface clock is derived from the P_CLK. Decreasing the frequency of P_CLK causes a proportional decrease in the I C serial clock and affects the I C timers. The timer values can be re-programmed during boot loading but the changes does not take effect until after the boot load has completed.
Page 500 B. Clocking > P_CLK Programming • Period (START_SETUP) = (START_SETUP * Period(PCLK)) — PCLK is 10ns — Reset time is 4.71 microseconds. — Tsi576 reset value is 0x01D7 START_HOLD Count for the START Condition Hold Period The START_HOLD field defines the minimum hold time for the START condition; that is, from I2C_SD seen low to I2C_SCLK pulled low.
Page 501 B. Clocking > P_CLK Programming IDLE_DET Count for Idle Detect Period The IDLE_DET field is used in two cases. First, it defines the period after reset during which the I2C_SCLK signal must be seen high in order to call the bus idle. This period is needed to avoid interfering with an ongoing transaction after reset.
Page 502 B. Clocking > P_CLK Programming B.2.3.5 I2C_SCLK High and Low Timing Register The I2C_SCLK High and Low Timing Register programs the nominal high and low periods of the I2C_SCLK signal when generated by the master interface. It is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM.
Page 503 B. Clocking > P_CLK Programming SCL_MINL Count for I2C_SCLK Low Minimum Period The SCL_MINL defines the minimum low period of the clock, from falling edge seen low to rising edge of I2C_SCLK. This is a master-only parameter. The actual observed period may be longer if other devices pull the clock low. •...
Page 504 B. Clocking > P_CLK Programming B.2.3.8 I2C Byte/Transaction Timeout Register The I2C Byte/Transaction Timeout Register programs the Transaction and Byte time-outs. The timer periods are relative to the USDIV period for the byte timeout, and relative to the MSDIV period for the transaction timeout.
Page 505: Other Performance Factors
B. Clocking > P_CLK Programming When the timer expires, either the BLTO or DTIMER event is generated, depending on whether the boot load sequence is active. If FREERUN is set to 1 when timer expires, then the timer is restarted immediately (the event is still generated), providing a periodic interrupt capability.
Page 506 B. Clocking > P_CLK Programming Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 507: Prbs Scripts
PRBS Scripts The following sections show the PRBS scripts used in “Using PRBS Scripts for the Transmitters and Receivers”. All of the PRBS scripts affect all of the ports, therefore editing the files to comment out the respective transmitting and receiving ports is required. Topics discussed include the following: •...
Page 508 C. PRBS Scripts > Tsi576_start_prbs_all.txt Script w 1e4a0 00000002 w 1e4e0 00000002 //Port 6 w 1e620 00000002 //Start 2^7 Pattern Generator w 1e660 00000002 w 1e6a0 00000002 w 1e6e0 00000002 //Port 8 w 1e820 00000002 //Start 2^7 Pattern Generator w 1e860 00000002 w 1e8a0 00000002 w 1e8e0 00000002 //Port a...
Page 509: Tsi576_Framer_Disable.txt Script
C. PRBS Scripts > Tsi576_framer_disable.txt Script Tsi576_framer_disable.txt Script This script turns off the word alignment framer because PRBS patterns are not word aligned. This script is only for use with PRBS patterns. In this script, the HALF_RATE bit is set corresponding to port operation at 1.25 Gbps. PRBS testing at 2.5 or 3.125 Gbps requires the HALF_RATE bit to be cleared.
Page 510: Tsi576_Sync_Prbs_All.txt Script
C. PRBS Scripts > Tsi576_sync_prbs_all.txt Script w 138b8 A03CE511 w 138bc A03CE511 //Port a w 13ab0 A03CE511 //Clear RX_ALIGN_EN w 13ab4 A03CE511 w 13ab8 A03CE511 w 13abc A03CE511 //Port c w 13cb0 A03CE511 //Clear RX_ALIGN_EN w 13cb4 A03CE511 w 13cb8 A03CE511 w 13cbc A03CE511 //Port e w 13eb0 A03CE511 //Clear RX_ALIGN_EN...
Page 511 C. PRBS Scripts > Tsi576_sync_prbs_all.txt Script w 1e0b0 00000002 w 1e0f0 00000002 //Port 2 w 1e230 0000000a //Sync pattern matcher w 1e270 0000000a w 1e2b0 0000000a w 1e2f0 0000000a w 1e230 00000002 w 1e270 00000002 w 1e2b0 00000002 w 1e2f0 00000002 //Port 4 w 1e430 0000000a //Sync pattern matcher w 1e470 0000000a...
Page 512 C. PRBS Scripts > Tsi576_sync_prbs_all.txt Script //Port 8 w 1e830 0000000a //Sync pattern matcher w 1e870 0000000a w 1e8b0 0000000a w 1e8f0 0000000a w 1e830 00000002 w 1e870 00000002 w 1e8b0 00000002 w 1e8f0 00000002 //Port a w 1ea30 0000000a //Sync pattern matcher w 1ea70 0000000a w 1eab0 0000000a w 1eaf0 0000000a...
Page 513: Tsi576_Read_Prbs_All.txt Script
C. PRBS Scripts > Tsi576_read_prbs_all.txt Script w 1ee70 0000000a w 1eeb0 0000000a w 1eef0 0000000a w 1ee30 00000002 w 1ee70 00000002 w 1eeb0 00000002 w 1eef0 00000002 Tsi576_read_prbs_all.txt Script This script is used to read the PRBS values. Note that the PRBS error counter and overflow bit fields must be read twice to determine the correct value.
Page 514 C. PRBS Scripts > Tsi576_read_prbs_all.txt Script //Port4 r 1e430 r 1e430 r 1e470 r 1e470 r 1e4b0 r 1e4b0 r 1e4f0 r 1e4f0 //Port6 r 1e630 r 1e630 r 1e670 r 1e670 r 1e6b0 r 1e6b0 r 1e6f0 r 1e6f0 //Port8 r 1e830 r 1e830...
Page 515 C. PRBS Scripts > Tsi576_read_prbs_all.txt Script r 1ea30 r 1ea70 r 1ea70 r 1eab0 r 1eab0 r 1eaf0 r 1eaf0 //Portc r 1ec30 r 1ec30 r 1ec70 r 1ec70 r 1ecb0 r 1ecb0 r 1ecf0 r 1ecf0 //Porte r 1ee30 r 1ee30 r 1ee70 r 1ee70...
Page 516 C. PRBS Scripts > Tsi576_read_prbs_all.txt Script Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 517: Eeprom Scripts
EEPROM Scripts The following section shows the EEPROM script used in “Modification by EEPROM Boot Load”. Script ew 0 0047FFFF ew 4 FFFFFFFF ew 8 138c8 ew c 7FFF0012 ew 10 138c0 ew 14 CA060084 ew 18 138B0 ew 1c 203CA513 ew 20 138B4 ew 24 203CA513 ew 28 138B8...
Page 518 D. EEPROM Scripts > Script ew 40 138B4 ew 44 203C2513 ew 48 138B8 ew 4c 203C2513 ew 50 138BC ew 54 203C2513 /B -- ew 58 138B0 ew 5c 200C2513 ew 60 138B4 ew 64 200C2513 ew 68 138B8 ew 6c 200C2513 ew 70 138BC ew 74 200C2513...
Page 519 D. EEPROM Scripts > Script ew 90 138c0 ew 94 CA060045 ew 98 138c0 ew 9c CA060005 ew a0 138c0 ew a4 4A060005 ew a8 138c0 ew ac CA060005 /16 -- ew b0 138c0 ew b4 CA060085 ew b8 138B0 ew bc 203C2513 ew c0 138B4 ew c4 203C2513...
Page 520 D. EEPROM Scripts > Script ew e0 138B4 ew e4 203CA513 ew e8 138B8 ew ec 203CA513 ew f0 138BC ew f4 203CA513 ew f8 138B0 ew fc 203CE513 ew 100 138B4 ew 104 203CE513 ew 108 138B8 ew 10c 203CE513 ew 110 138BC ew 114 203CE513 ew 118 138c8...
Page 521 D. EEPROM Scripts > Script ew 130 136B0 ew 134 203CA513 ew 138 136B4 ew 13c 203CA513 ew 140 136B8 ew 144 203CA513 ew 148 136BC ew 14c 203CA513 ew 150 136B0 ew 154 203C2513 ew 158 136B4 ew 15c 203C2513 ew 160 136B8 ew 164 203C2513 ew 168 136BC...
Page 522 D. EEPROM Scripts > Script ew 180 136B8 ew 184 200C2513 ew 188 136BC ew 18c 200C2513 ew 190 136c0 ew 194 CA060004 ew 198 136c0 ew 19c CA060044 ew 1a0 136C4 ew 1a4 002C0545 ew 1a8 136c0 ew 1ac CA060045 ew 1b0 136c0 ew 1b4 CA060005 ew 1b8 136c0...
Page 523 D. EEPROM Scripts > Script ew 1d0 136B0 ew 1d4 203C2513 ew 1d8 136B4 ew 1dc 203C2513 ew 1e0 136B8 ew 1e4 203C2513 ew 1e8 136BC ew 1ec 203C2513 ew 1f0 136B0 ew 1f4 203CA513 ew 1f8 136B4 ew 1fc 203CA513 ew 200 136B8 ew 204 203CA513 ew 208 136BC...
Page 524 D. EEPROM Scripts > Script ew 220 136B8 ew 224 203CE513 ew 228 136BC ew 22c 203CE513 ew 230 136c8 ew 234 7FFF0002 ew 238 8 ew 23c deadbeef Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 525: Index
Index Multicast Maximum Latency Timer Silent Discard of Packets Event Notification Interrupt Notifications Numerics Overview 1x + 1x Configuration Port-Write Notifications 4x + 0x Configuration RapidIO Error Rate Events Arbitration for Multicast Engine Ingress Port Fabric Interrupt Status Register Fixed-Pattern BERT, Transmitter Configuration Functional Overview Walkthrough Bit Error Rate Testing (BERT)
Page 526 Index Loopbacks Port Power-up and Power-down Loss of Lane Synchronization Port Reset Dead Link Timer Port Width Override Port-Write Notifications Power Down Configuration and Operation Through Power Down Maintenance Packets Power-up Option Signals Multicast Power-up Options Arbitration for Multicast Engine Ingress Port Default Port Speed Error Management of Multicast Packets Port Power-up and Power-down...
Page 527 Index Overview Serial RapidIO Protocol Packets Physical Layer Serial RapidIO Protocol Overview Signal Signal Groupings Clock and Reset Interrupts JTAG / TAP Controller Multicast Power Supplies Serial Port Configuration Serial Port Lane Ordering Select Serial Port Receive Serial Port Speed Select Serial Port Transmit Signal Types Signals...
Page 528 Index Tsi576 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 529 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 srio@idt.com San Jose, CA 95138 www.idt.com June 6, 2016...
Page 530 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.