Renesas IDT 89HPES16T7 Manuals

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Renesas IDT 89HPES16T7 User Manual (179 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 3 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
7
PES16T7 Device Overview
19
Introduction
19
List of Features
19
System Diagrams
21
Table 1.1 Table
21
Logic Diagram
22
System Identification
23
Vendor ID
23
Device ID
23
Revision ID
23
Jtag ID
23
Ssid/Ssvid
23
Device Serial Number Enhanced Capability
23
Pin Description
24
Table 1.3 PCI Express Interface Pins
24
Table 1.4 Smbus Interface Pins
25
Table 1.5 General Purpose I/O Pins
25
Table 1.6 System Pins
26
Table 1.7 Test Pins
27
Table 1.8 Power and Ground Pins
28
Pin Characteristics
29
Table 1.9 Pin Characteristics
29
Port Configuration
30
Clocking, Reset, and Initialization
33
Introduction
33
Initialization
33
Table 2.1 Reference Clock Mode Encoding
33
Table 2.2 Boot Configuration Vector Signals
35
Reset
36
Fundamental Reset
36
Hot Reset
38
Upstream Secondary Bus Reset
39
Downstream Secondary Bus Reset
39
Downstream Port Reset Outputs
40
Power Enable Controlled Reset Output
40
Power Good Controlled Reset Output
41
Theory of Operation
43
Introduction
43
Table 3.1 IFB Buffer Sizes
43
Data Paths
44
Table 3.2 PES16T7 Buffer Sizes
44
Table 3.3 Bus Decoupler Queue and Insertion Buffer Size
44
Store-And-Forward Vs. Cut-Through Switching and Latency
45
Switch Core
45
Table 3.4 Latency
45
Transaction Routing
46
Transaction Reordering
47
Table 3.5 Switch Routing Methods
47
Table 3.6 IFB Transaction Ordering
47
Scheduling and Port Arbitration
48
Peer-To-Peer Transactions
50
Bus Locking
51
Port Interrupts
52
Legacy Interrupt Emulation
53
Table 3.7 Downstream Port Interrupts
53
Standard Pcie Error Detection and Handling
54
Physical Layer Errors
54
Data Link Layer Errors
54
Table 3.8 PES16T7 Downstream to Upstream Port Interrupt Routing
54
Table 3.9 Physical Layer Errors
54
Transaction Layer Errors
55
Table 3.10 Data Link Layer Errors
55
Table 3.11 Transaction Layer Errors
55
Table 3.12 Ingress Malformed TLP Error Checks
56
Routing Errors
57
Table 3.13 Egress Malformed TLP Error Checks
57
Switch Specific Error Detection and Handling
58
Switch Time-Outs
58
End-To-End Parity Checking
59
TLP Processing
60
Port 1 Performance Characteristics
61
Link Operation
63
Introduction
63
Polarity Inversion
63
Link Width Negotiation
63
Lane Reversal
63
Link Retraining
67
Link down
68
Slot Power Limit Support
68
Upstream Port
68
Downstream Port
68
Link States
68
Active State Power Management
69
Link Status
70
General Purpose I/O
71
GPIO Configuration
71
Table 5.1 General Purpose I/O Pin Alternate Function
71
GPIO Pin Configured as an Input
72
GPIO Pin Configured as an Output
72
GPIO Pin Configured as an Alternate Function
72
Table 5.2 GPIO Pin Configuration
72
Smbus Interfaces
73
Introduction
73
Master Smbus Interface
74
Initialization
74
Serial EEPROM
74
Table 6.1 Serial EEPROM Smbus Address
74
Table 6.2 PES16T7 Compatible Serial Eeproms
75
Table 6.3 Serial EEPROM Initialization Errors
77
I/O Expanders
78
Table 6.4 I/O Expander Function Allocation
78
Table 6.5 I/O Expander 0 Signals
81
Table 6.6 I/O Expander 1 Signals
82
Table 6.7 I/O Expander 2 Signals
82
Table 6.8 I/O Expander 3 Signals
83
Slave Smbus Interface
84
Initialization
84
Table 6.9 I/O Expander 4 Signals
84
Table 6.10 Slave Smbus Address When a Static Address Is Selected
84
Smbus Transactions
85
Table 6.11 Slave Smbus Command Code Fields
85
Table 6.12 CSR Register Read or Write Operation Byte Sequence
86
Table 6.13 CSR Register Read or Write CMD Field Description
87
Table 6.14 Serial EEPROM Read or Write Operation Byte Sequence
88
Table 6.15 Serial EEPROM Read or Write CMD Field Description
88
Power Management
93
Introduction
93
PME Messages
94
Power Express Power Management Fence Protocol
94
Table 7.1 PES16T7 Power Management State Transition Diagram
94
Power Budgeting Capability
95
Notes
97
Hot-Plug and Hot-Swap
97
Introduction
97
Table 8.1 Downstream Port Hot-Plug Signals
99
Hot-Plug I/O Expander
100
Hot-Plug Interrupts and Wake-Up
100
Legacy System Hot-Plug Support
100
Hot-Swap
102
Configuration Registers
103
Introduction
103
Table 9.1 Base Addresses for Port Configuration Space Registers
103
Upstream Port (Port 0)
105
Table 9.2 Upstream Port 0 Configuration Space Registers
105
Downstream Ports (Ports 1 through 6)
110
Table 9.3 Downstream Ports 1 through 6 Configuration Space Registers
110
Register Definitions
114
Type 1 Configuration Header Registers
114
PCI Express Capability Structure
123
Power Management Capability Structure
135
Message Signaled Interrupt Capability Structure
137
Subsystem ID and Subsystem Vendor ID
138
Extended Configuration Space Access Registers
139
Advanced Error Reporting (AER) Enhanced Capability
139
Device Serial Number Enhanced Capability
145
PCI Express Virtual Channel Capability
146
Power Budgeting Enhanced Capability
151
Switch Control and Status Registers
152
Internal Switch Error Control and Status Registers
164
JTAG Boundary Scan
169
Introduction
169
Test Access Point
169
Signal Definitions
169
Table 10.1 JTAG Pin Descriptions
170
Boundary Scan Chain
171
Table 10.2 Boundary Scan Chain
171
Test Data Register (DR)
172
Boundary Scan Registers
172
Instruction Register (IR)
174
Extest
175
Sample/Preload
175
Bypass
175
Table 10.3 Instructions Supported by Pes16T7'S JTAG Boundary Scan
175
Clamp
176
Idcode
176
Validate
176
Reserved
176
Usage Considerations
176

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