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IDT Link Operation
Notes
PES4T4 User Manual
L0s
Figure 4.1 PES4T4 ASPM Link Sate Transitions
Active State Power Management
The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi-
tions are initiated by hardware without software involvement.
The PES4T4 ASPM supports the required L0s state as well as the optional L1 state. The L0s Entry
Timer (L0ET) field in the PCI Power Management Proprietary Control (PMPC) register controls the amount
of time L0s entry conditions must be met before the hardware transitions the link to the L0s state.
– The upstream switch port has the following L0s entry conditions.
The receive lane of all of the switch downstream ports which are not in a low power state (i.e., D3)
and whose link is not down are in the L0s state.
The switch has no TLPs to transmit on the upstream port or there are no available flow control
credits to transmit a TLP.
There are no DLLPs pending for transmission on the upstream port.
– The downstream switch ports have the following L0s entry conditions.
The receive lane of the switch upstream port is in the L0s state.
The switch has no TLPs to transmit on the downstream port or there are no available flow control
credits to transmit a TLP.
There are no DLLPs pending for transmission on the downstream port.
The L1 Entry Timer (L1ET) field in the PCI Power Management Proprietary Control (PMPC) register
controls the amount of time L1 entry conditions must be met before the hardware transitions the link to the
L1 state. If these conditions are met and the link is in the L0 or L0s states, the hardware will request a tran-
L1
L0
L2/L3 Ready
L2
L3
4 - 3
Fundamental Reset
Hot Reset
Etc.
Link Down
February 1, 2011
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