Internal Errors - Renesas IDT 89HPES48H12G2 User Manual

IDT Switch Core
Notes
PES48H12G2 User Manual
If the number of data DWords is zero, then the completion size is estimated to be three DWords (i.e., a
0:13:3 representation value of 0x0018).
– Otherwise, if the number of required data DWords is less than the Constant Limit (CNSTLIMIT)
field in the RMCTL register, then the completion size is estimated as the number of required data
DWords plus one.
– Otherwise, if the number of required data DWords is greater than CNSTLIMIT, then the completion
size is estimated using OverheadDWords as described below.
OverheadDWords represents the number of DWords of link overhead. This includes the header, data
link layer overhead, and physical layer overhead of the completion TLP(s) associated with this request.
Ideally, OverheadDWords would be set to the number of completion TLPs associated with the request
multiplied by the TLP overhead. Unfortunately, this requires a multiplication. Therefore, the following esti-
mate may be used.
A completion header is 3 DWords. There are 2 DWords of additional overhead associated with a TLP.
Therefore a reasonable estimate of the overhead is 5 DWords. In many systems, completions are 64-bytes
in size (i.e., 16 DWords in size).
OverheadDWords = (Length / 16) * 5.
– This is approximately equal to OverheadDWords = (Length / 16) * 4.
– This may be simplified to (Length / 4) and may be computed as (Length >> 2).
Thus, an acceptable value for OverheadFactor in many systems is 2. The OverheadFactor value used in
computing the completion size estimate is contained in the Overhead Factor (OVRFACTOR) field in the
RMCTL register.

Internal Errors

Internal errors are errors associated with a PCI Express interface that occurs within a component and
which may not be attributable to a packet or event on the PCI Express interface itself or on behalf of trans-
actions initiated on PCI Express.
The PES48H12G2 classifies the following IDT proprietary switch errors as internal errors.
– Switch core time-outs
– Single and double bit internal memory ECC errors
– End-to-end data path parity protection errors
Internal errors are reported by the port in which they are detected through AER as outlined in the PCI-
SIG Internal Error Reporting ECN. The reporting of internal errors may be disabled by clearing the Internal
Error Reporting Enable (IERROREN) bit in the port's Internal Error Reporting Control (IERRORCTL)
register. When internal error reporting is disabled, the following AER fields become read-only:
– Uncorrectable Internal Error Mask (UIE) field in the AERUEM register
– Uncorrectable Internal Error Severity (UIE) field in the AERUESV register
– Correctable Internal Error Mask (CIE) field in the AERCEM register
– Header Log Overflow Mask (HLO) field in the AERCEM register
The PES48H12G2 does not support recording of headers for uncorrectable internal errors. When an
uncorrectable internal error is reported by AER, a header of all ones is recorded.
Corresponding to each possible internal error source is a status bit in the Internal Error Reporting Status
(IERRORSTS) register. A bit is set in the status register when the corresponding internal error is detected.
Associated with each internal error status bit in the IERRORSTS register is a mask bit in the Internal Error
Reporting Mask (IERRORMSK) register. When a mask bit is set in this register, the setting of the corre-
sponding status bit is masked from generating an internal error.
Each internal error status bit has an associated severity bit in the IERRORSEV register. When an
unmasked internal error is detected, the error is reported as dictated by the corresponding severity bit (i.e.,
either an Uncorrectable Internal Error or a Correctable Internal Error). When an uncorrectable or correct-
able internal error is reported, the corresponding AER status bit is set and process as dictated by the PCIe
base specification and Internal Error Reporting ECN.
3 - 13 April 5, 2013