Page 1 ® 89HPES4T4 ™ PCI Express® Switch Preliminary User Manual February 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc.
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: About This Manual
About this Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES4T4, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan- dard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
Page 4: Numeric Representations
Notes To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included. Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition.
Page 5 Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Table 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Note: Software in the context of this register terminology refers to modifications made by PCIe root configuration writes to registers made through the serial EEPROM register initialization.
Page 6: Use Of Hypertext
Notes Type Abbreviation Description Read and Write when Software can read the register/bits with this attribute. Writing to Unlocked register/bits with this attribute will only cause the value to be modified if the REGUNLOCK bit in the SWCNTL register is set. When the REGUNLOCK bit is cleared, writes are ignored and the register/bits are effectively read-only.
Page 7 Notes July 16, 2007: Made numerous minor edits throughout manual. Removed all references to slave SMBus. June 6, 2008: In Chapter 1, updated the Features section to include 10x10mm 132-pin package option. September 23, 2009: In Chapter 5, SMBus, added Note in I/O Expander section re setting of GPIO- FUNC[4:2] bits.
Page 8 Notes PES4T4 User Manual February 1, 2011...
Page 9: Table Of Contents
Table of Contents ® About this Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
Page 10 IDT Table of Contents Notes Polarity Inversion ..........................4-1 Link Width Negotiation........................4-1 Link Retraining..........................4-1 Link Down ............................4-1 Slot Power Limit Support ........................ 4-2 Upstream Port ........................4-2 Downstream Port........................4-2 Link States ............................4-2 Active State Power Management ....................4-3 Link Status ............................
Page 11 IDT Table of Contents Notes PCI Express Capability Structure ..................9-21 Power Management Capability Structure ................9-32 Message Signaled Interrupt Capability Structure ..............9-34 Subsystem ID and Subsystem Vendor ID ................9-35 Extended Configuration Space Access Registers ..............9-36 Advanced Error Reporting (AER) Enhanced Capability ............9-37 Device Serial Number Enhanced Capability.................
Page 12 IDT Table of Contents Notes PES4T4 User Manual February 1, 2011...
Page 13 List of Tables ® Table 1.1 PCI Express Interface Pins....................1-4 Notes Table 1.2 SMBus Interface Pins ......................1-4 Table 1.3 General Purpose I/O Pins....................1-5 Table 1.4 System Pins.........................1-5 Table 1.5 Test Pins..........................1-6 Table 1.6 Power and Ground Pins....................... 1-6 Table 1.7 Pin Characteristics.......................
Page 14 IDT List of Tables Notes PES4T4 User Manual February 1, 2011...
Page 15 List of Figures ® Figure 1.1 PES4T4 Architectural Block Diagram ................1-2 Notes Figure 1.2 PES4T4 Logic Diagram .....................1-3 Figure 1.3 PES4T4 Port Configuration ....................1-9 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
Page 16 IDT List of Figures Notes PES4T4 User Manual viii February 1, 2011...
Page 17 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-40 AERCTL - AER Control (0x118)......................9-41 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
Page 18 IDT Register List Notes PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-21 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-31 PCIEDCTL - PCI Express Device Control (0x048)..................9-22 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-31 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-23 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................9-31 PCIELCAP - PCI Express Link Capabilities (0x04C) ................9-24 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .................9-31...
Page 19 IDT Register List Notes SWTOCTL - Switch Time-Out Control (0x4E4)..................9-62 SWTORCTL - Switch Time-Out Reporting Control (0x4E8)..............9-62 VCR0CAP- VC Resource 0 Capability (0x210)..................9-45 VCR0CTL- VC Resource 0 Control (0x214)....................9-46 VCR0STS - VC Resource 0 Status (0x218)....................9-47 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............9-47 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............9-48 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............9-48 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C) .............9-49...
Page 20 IDT Register List Notes PES4T4 User Manual February 1, 2011...
Page 21: Pes4T4 Device Overview
Chapter 1 PES4T4 Device Overview ® Introduction Notes The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral chip that performs PCI Express Base switching. It provides connec- tivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports.
Page 22: System Diagrams
IDT PES4T4 Device Overview Notes 5 General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Each pin has a selectable alternate function Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing System Diagrams...
Page 23: Logic Diagram
IDT PES4T4 Device Overview Logic Diagram PCI Express PEREFCLKP Switch Reference PE0TP[0] PEREFCLKN SerDes Output Clocks PE0TN[0] Port 0 PCI Express PE0RP[0] Switch PCI Express PE2TP[0] SerDes Input PE0RN[0] Switch Port 0 SerDes Output PE2TN[0] Port 2 PCI Express PE2RP[0] Switch PE2RN[0] SerDes Input...
Page 24: Pin Description
IDT PES4T4 Device Overview Pin Description Notes The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
Page 25: Table 1.3 General Purpose I/O Pins
IDT PES4T4 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] General Purpose I/O.
Page 26: Table 1.5 Test Pins
IDT PES4T4 Device Overview Notes Signal Type Name/Description RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES4T4 executes the reset procedure and remains in a reset state with the Master SMBus active. This allows software to read and write registers internal to the device before normal device operation begins.
Page 27: Pin Characteristics
IDT PES4T4 Device Overview Pin Characteristics Notes Note: Some input pads of the PES4T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Page 28: System Identification
IDT PES4T4 Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES4T4 device ID is shown in Table 1.8. PCIe Device Device ID 0x803A Table 1.8 PES4T4 Device ID...
Page 29: Figure 1.3 Pes4T4 Port Configuration
IDT PES4T4 Device Overview Notes Port 0 Dev. 0 PES4T4 PCI to PCI Bridge Virtual PCI Bus Dev. 2 Dev. 3 Dev. 4 PCI to PCI PCI to PCI PCI to PCI Bridge Bridge Bridge Port 3 Port 4 Port 2 Figure 1.3 PES4T4 Port Configuration PES4T4 User Manual 1 - 9...
Page 30 IDT PES4T4 Device Overview Notes PES4T4 User Manual 1 - 10 February 1, 2011...
Page 31: Clocking, Reset, And Initialization
Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES4T4 has a differential reference clock input that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. The frequency of the reference clock is 100MHz. The reference clock differential inputs feeds several on-chip PLLs.
Page 32: Figure 2.2 Non-Common Clock On Upstream; Common Clock On Downstream
IDT Clocking, Reset, and Initialization Clock Operation Notes Port 2 PES4T4 Port 0 Root Complex Port 4 CCLKUS CCLKDS PEREFCLK Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock) Port 2 PES4T4 Port 0 Root Complex...
Page 33: Figure 2.4 Non-Common Clock On Upstream And Downstream
IDT Clocking, Reset, and Initialization Clock Operation Notes PES4T4 Port 2 Port 0 Root Complex Port 4 CCLKUS CCLKDS PEREFCLK Clock Generator * Clock Generator Clock Generator * May be unique for each EP Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.1 is sampled by the PES4T4 during a fundamental reset when PERSTN is negated.
Page 34: Reset
IDT Clocking, Reset, and Initialization Clock Operation Notes May Be Signal Description Overridden CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This pin is used as the initial value of the Slot Clock Configura- tion bit in all of the Link Status Registers for downstream ports.
Page 35: Fundamental Reset
IDT Clocking, Reset, and Initialization Clock Operation Fundamental Reset Notes A fundamental reset may be initiated by any of the following conditions: – A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input pin.
Page 36: Hot Reset
IDT Clocking, Reset, and Initialization Clock Operation Notes Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these side effects.
Page 37: Upstream Secondary Bus Reset
IDT Clocking, Reset, and Initialization Clock Operation Notes When a hot reset occurs, the following sequence is executed. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets with the hot reset bit set. All of the logic associated with the PES4T4 is reset except the PLLs, SerDes, and master SMBus interface.
Page 38: Downstream Secondary Bus Reset
IDT Clocking, Reset, and Initialization Clock Operation Notes When an upstream secondary bus reset occurs, the following sequence is executed. 1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set. 2.
Page 39: Power Good Controlled Reset Output
IDT Clocking, Reset, and Initialization Clock Operation Notes PWR2RST RST2PWR PxPEP PxRSTN Figure 2.6 Power Enable Controlled Reset Output Mode Operation While slot power is disabled, the corresponding downstream port reset output is asserted. When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated.
Page 40: Hot Reset Controlled Reset Output
IDT Clocking, Reset, and Initialization Clock Operation Notes If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is detected (i.e., PxPWRGDN is negated), the corresponding port reset output is immediately asserted. Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profiled power level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN).
Page 41: Theory Of Operation
Chapter 3 Theory of Operation ® Port Interrupts Notes The upstream port (Port 0) generates legacy interrupts and MSIs to report internal switch errors such as parity errors and errors in reading configuration registers. Downstream ports support generation of legacy interrupts and MSIs.
Page 42: Table 3.2 Pes4T4 Downstream To Upstream Port Interrupt Routing
IDT Theory of Operation Notes The PES4T4 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through D) at each port. – The value of the INTA, INTB, INTC and INTD aggregated state for the entire switch may be deter- mined by examining the corresponding field in the upstream port’s Interrupt Status (P0_INTSTS) register.
Page 43: Link Operation
Chapter 4 Link Operation ® Introduction Notes The PES4T4 is a 4 port switch device. The upstream port link width is configured as a x1 link width and all three downstream ports are also configured as x1 link widths. Polarity Inversion Each port of the PES4T4 supports automatic polarity inversion as required by the PCIe specification.
Page 44: Slot Power Limit Support
IDT Link Operation Slot Power Limit Support Notes The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream switch port or root port to the upstream port of a connected device or switch. Upstream Port When a Set_Slot_Power_Limit message is received by the upstream switch port, the fields in the message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
Page 45: Active State Power Management
IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.1 PES4T4 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.
Page 46: Link Status
IDT Link Operation Notes sition to the L1 state from its link partner. Note that L1 entry requests are only made by the PES4T4 upstream port. If the link partner acknowledges the transition, the L1 state is entered. Otherwise the L0s state is entered.
Page 47: General Purpose Inputs/Outputs
Chapter 5 General Purpose Inputs/Outputs ® Introduction Notes The PES4T4 has five General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.
Page 48: Gpio Pin Configured As An Output
IDT General Purpose Inputs/Outputs GPIO Pin Configured as an Output Notes When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the value in the corresponding bit position of the GPIOD register is driven on the pin. System designers should treat the GPIO outputs as asynchronous outputs.
Page 49 IDT General Purpose Inputs/Outputs PES4T4 User Manual 5 - 3 February 1, 2011...
Page 50 IDT General Purpose Inputs/Outputs PES4T4 User Manual 5 - 4 February 1, 2011...
Page 51 IDT General Purpose Inputs/Outputs PES4T4 User Manual 5 - 5 February 1, 2011...
Page 52 IDT General Purpose Inputs/Outputs Notes PES4T4 User Manual 5 - 6 February 1, 2011...
Page 53: Smbus Interfaces
Chapter 6 SMBus Interfaces ® Introduction Notes The PES4T4 contains one SMBus interface. The master SMBus interface provides a connection for an optional external serial EEPROM used for initialization and optional external I/O expanders. Two pins make up the master SMBus interface: the SMBus clock pin and the SMBus data pin. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.
Page 54: Figure 6.1 Single Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes Serial EEPROM Size 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.1 PES4T4 Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM address rolls over from 0xFFFF to 0x0.
Page 55: Figure 6.2 Sequential Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.2 Sequential Double Word Initialization Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end...
Page 56: Table 6.2 Serial Eeprom Initialization Errors
IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence. The correct result should always be 0xFF (i.e., all ones).
Page 57: I/O Expanders
IDT SMBus Interfaces Notes Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results. SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the SMBus Status (SMBUSSTS) register.
Page 58: Table 6.4 I/O Expander Default Output Signal Value
IDT SMBus Interfaces Notes SMBus I/O Defaul Expander Signal Description t Value (I/O-x.4) P2AIN Attention indicator output (off) (I/O-x.5) P2PIN Power indicator output (on) (I/O-x.6) P2PEP Power enable output (on) (I/O-x.7) P2ILOCKP Electromechanical interlock (negated - off) Table 6.4 I/O Expander Default Output Signal Value The following I/O expander configuration sequence is issued by the PES4T4 to I/O expanders zero and one (i.e., the ones that contain hot-plug signals).
Page 59 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES4T4 to I/O expander four (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
Page 60: Table 6.5 I/O Expander 0 Signals
IDT SMBus Interfaces Notes Writing a one to the Reload I/O Expander Signals (RELOADIOEX) bit in the IOEXPINTF register causes the PES4T4 to generate SMBus write and read transactions to the I/O expander number selected in the SEL field. This results in the value of the IOEDATA field being updated to reflect the current state of the corresponding I/O expander signals.
Page 61: Table 6.6 I/O Expander 1 Signals
IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 10 (I/O-1.2) P4PFN Port 4 power fault input 11 (I/O-1.3) P4MRLN Port 4 manually-operated retention latch (MRL) input 12 (I/O-1.4) P4AIN Port 4 attention indicator output 13 (I/O-1.5) P4PIN Port 4 power indicator output 14 (I/O-1.6) P4PEP Port 4 power enable output...
Page 62: Table 6.7 I/O Expander 2 Signals
IDT SMBus Interfaces Notes I/O Expander 2 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) Reserved Tie High 1 (I/O-0.1) Reserved Tie High 2 (I/O-0.2) Reserved Tie High 3 (I/O-0.3) Reserved Tie High 4 (I/O-0.4) Reserved Tie High or Low 5 (I/O-0.5) Reserved Tie High or Low...
Page 63 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 12 (I/O-1.4) P4ACTIVEN Port 4 activity output 13 (I/O-1.5) Reserved Tie High or Low 14 (I/O-1.6) Reserved Tie High or Low 15 (I/O-1.7) Reserved Tie High or Low Table 6.8 I/O Expander 4 Signals (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Page 64 IDT SMBus Interfaces Notes PES4T4 User Manual 6 - 12 February 1, 2011...
Page 65: Power Management
Chapter 7 Power Management ® Introduction Notes The PES4T4 supports the following device power management states: D0 Uninitialized, D0 Active, , and D3 . A power management state transition diagram for the states supported by the PES4T4 Cold is provided in Figure 7.1 and described in Table 7.1. A power management capability structure is located in the configuration space of each PCI-PCI bridge in the PES4T4.
Page 66: Pme Messages
IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software. D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.
Page 67: Power Express Power Management Fence Protocol
IDT Power Management Power Express Power Management Fence Protocol Notes The Root complex takes the following steps to turn off power to a system: – The root places all devices in the D3 state – Upon entry to D3 , all devices transition their links to the L1 state –...
Page 68: Wakeup Protocol
IDT Power Management Notes register. When the PWRBDVUL bit is cleared, these register are read-only and writes to these registers are ignored. To enable the power budgeting capability, the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM. Wakeup Protocol The PES4T4 supports the PCIe link wakeup protocol when the following conditions are met: –...
Page 69: Waken Signal As An Input
IDT Power Management WAKEN Signal as an Input Notes The WAKEN signal may be configured as an input to make use of the PES4T4’s ability to translate WAKEN input to Beacon transmission (on the upstream link). To enable this feature, the following must be true: –...
Page 70: Auxiliary Power Control
IDT Power Management Notes In Device OFF state, both main power and the auxiliary power is off. The device enters Inactive Standby when the auxiliary power is applied and Main Power is Off. When main power is applied the device enters the Device ON state. As shown in Figure 7.3, when main power is applied for the first time after auxiliary power is switched ON, the external POR circuitry is required to assert PERSTN and sequence the APWRDISN signal with respect to PERSTN .
Page 71: Figure 7.3 L2 Mode Enable/Disable And Frsticky Bit Initialization
IDT Power Management Notes APWRDISN PERSTN 256 Clks 8 Clks a. L2 Mode Enabled, FRSticky bits initialized APWRDISN (High) PERSTN 256 Clks 8 Clks b. L2 Mode Enabled, FRSticky bits not initialized APWRDISN (Low) PERSTN 256 Clks 8 Clks b. L2 Mode Disabled Figure 7.3 L2 Mode Enable/Disable and FRSticky Bit Initialization If the APWRDISN signal is inactive (High) 256 clocks after de-assertion of the fundamental reset, the Auxiliary Power Enable (APWREN) bit is set in the SWCTL register.
Page 72: Pes4T4 Auxiliary Power Usage
IDT Power Management Notes turned ON using in-band beacon or out-of-band WAKEN signaling when the traffic resumes). The signal is sampled High, resulting in retention of the state of the FRSticky bits. The APWRDISN signal input is sampled again 256 clock cycles after de-assertion of the fundamental reset (PERSTN). A high state of this signal continues to set the APWREN bit in the SWCTL register.
Page 73: Table 7.2 Auxiliary Power Enabled (Beacon Off)
IDT Power Management Notes Current Estimate Item Comment (mA) 3.3 V IO Power In L2 mode, auxiliary power supply is Supply used to power up all the I/Os. Rambus L2 (2 Ser- Des quads ON with Beacon OFF in both the SerDes) Core Logic 3.3 V I/O Regulator Leakage...
Page 74: Figure 7.5 Conceptual Diagram Of The Pes4T4 Auxiliary Power Connection
IDT Power Management Notes 3.3 V Regulator VDDIO VDDCORE +12V 1.0 V VDDAPE Switcher Regulator VDDPE PES4T4 1.5 V VTTPE Regulator Regulator 3.3 Vaux Power Voltage 1.0 V Regulator 1.5 V Figure 7.5 Conceptual Diagram of the PES4T4 Auxiliary Power Connection When the device enters the Active standby mode, the auxiliary voltage powers the V CORE, V APE,...
Page 75: Hot-Plug And Hot-Swap
Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES4T4 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
Page 76: Figure 8.2 Hot-Plug With Switch On Add-In Card Application
IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES4T4 Port x Port y PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES4T4 Master SMBus Clock and Data Port x Port y...
Page 77 IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES4T4 in an application in which one or more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a down- stream slot.
Page 78: Hot-Plug I/O Expander
IDT Hot-Plug and Hot-Swap Notes When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.
Page 79: Figure 8.4 Pes4T4 Hot-Plug Event Signalling
IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.
Page 80: Hot-Swap
IDT Hot-Plug and Hot-Swap Hot-Swap Notes The PES4T4 is hot-swap capable and meets the following requirements – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, Master SMBus clock and data, etc.). – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.
Page 81: Configuration Registers
Chapter 9 Configuration Registers ® Configuration Space Organization Notes Each software visible register in the PES4T4 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES4T4 that cannot be accessed by the root. Each software visible register in the PES4T4 has a system address.
Page 82: Pci Express Capability Structure
IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting Enhanced Capability 0x328 Switch Control...
Page 83: Table 9.2 Upstream Port 0 Configuration Space Registers
IDT Configuration Registers Upstream Port (Port 0) Notes Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 9-11 0x002 Word P0_DID DID - Device Identification Register (0x002) on page 9-11 0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 9-11...
Page 84 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 9-19 0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 9-21 0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 9-21 0x048 Word P0_PCIEDCTL...
Page 85 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 9-41 0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 9-41 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9- 0x120 Dword P0_AERHL2DW...
Page 86 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x308 Dword P0_PWRBDV2 PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300) on page 9-50 0x30C Dword P0_PWRBDV3 PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300) on page 9-50 0x310 Dword P0_PWRBDV4 PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300) on page...
Page 87: Table 9.3 Downstream Ports 2 Through 5 Configuration Space Registers
IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x4E8 Dword P0_SWTORCTL SWTORCTL - Switch Time-Out Reporting Control (0x4E8) on page 9- 0x4EC Dword P0_SWTOCNT SWTOCNT - Switch Time-Out Count (0x4EC) on page 9-63 0x5CC Dword P0_WAKEUPCNT WAKEUPCNTL - Wakeup Protocol Control Register (0x5CC) on page 9-63 Table 9.2 Upstream Port 0 Configuration Space Registers (Part 5 of 5) Downstream Ports (Ports 2 through 4)
Page 88 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on page 9-18 0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-18 0x032 Word Px_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-18 0x034...
Page 89 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0D8 DWord Px_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) on page 9-35 0x0DC DWord Px_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) on page 9-35 0x0F0 Dword Px_SSIDSSVIDCA SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capabil-...
Page 90 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x280 Dword Px_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 9-49 0x284 Dword Px_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 9-50 0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-50 0x28C Dword Px_PWRBPBC...
Page 91 IDT Configuration Registers Register Definitions Notes Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-11. DID - Device Identification Register (0x002) Field Default...
Page 92 IDT Configuration Registers Notes Field Default Type Description Field Name Value PERRE Parity Error Enable. The Master Data Parity Error bit is set in the PCI Status register (PCISTS) if this bit is set and the bridge receives a poisoned completion or generates a poi- soned write.
Page 93 IDT Configuration Registers Notes Field Default Type Description Field Name Value FB2B Fast Back-to-Back (FB2B). Not applicable. MDPED RW1C Master Data Parity Error Detected. This bit is set when the PERRE bit is set in the PCI Command register and the bridge receives a poisoned completion or generates a poi- soned write request on the primary side of the bridge.
Page 94 IDT Configuration Registers Notes CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s functionality but may be read and written by software. This field is implemented for compatibility with legacy soft- ware.
Page 95 IDT Configuration Registers Notes PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary inter- face of the bridge is connected.
Page 96 IDT Configuration Registers Notes IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register. Reserved Reserved field.
Page 97 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable trans- actions between the primary and secondary interfaces of the bridge.
Page 98 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:4 PMLIMIT Prefetchable Memory Address Limit. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forwarding of prefetchable transactions between the primary and secondary interfaces of the bridge. This field contains A[31:20] of the highest memory address, with A[19:0] assumed to be 0xF_FFFF, that is below the primary interface of the bridge.
Page 99 IDT Configuration Registers Notes CAPPTR - Capabilities Pointer Register (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. This field specifies a pointer to the head of the capabilities structure. EROMBASE - Expansion ROM Base Address Register (0x038) Field Default Type...
Page 100 IDT Configuration Registers Notes Field Default Type Description Field Name Value SERRE System Error Enable. This bit controls forwarding of ERR_NONFATAL or ERR_FATAL from the secondary inter- face of the bridge to the primary interface. Note that error reporting must be enabled in the Command register or the PCI Express-specific bits are set in PCI Express Capability structure, Device Control register for errors to be reported on the primary interface.
Page 101 IDT Configuration Registers PCI Express Capability Structure Notes PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure. 15:8 NXTPTR 0xC0 Next Pointer.
Page 102 IDT Configuration Registers Notes Field Default Type Description Field Name Value 11:9 E1AL Endpoint L1 Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L1 state to the L0 state. The value is hardwired to 0x0 as this field does not apply to a switch.
Page 103 IDT Configuration Registers Notes Field Default Type Description Field Name Value FEREN Fatal Error Reporting Enable. This bit controls reporting of fatal errors. URREN Unsupported Request Reporting Enable. This bit controls reporting of unsupported requests. Enable Relaxed Ordering. When set, this bit enables relaxed ordering.
Page 104 IDT Configuration Registers Notes Field Default Type Description Field Name Value NFED RW1C Non-Fatal Error Detected. This bit indicates the status of correctable errors. Errors are logged in this register regard- less of whether error reporting is enabled or not. RW1C Fatal Error Detected.
Page 105 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:12 L0SEL see text L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express link. This field depends on whether a common or separate reference clock is used. When separate clocks are used, 1 us to 2 µs is reported with a read-only value of 0x5.
Page 106 IDT Configuration Registers Notes Field Default Type Description Field Name Value Read Completion Boundary. This field is not applicable and is hardwired to zero. LDIS Link Disable. When set in a downstream port, this bit dis- ables the link. This bit is not applicable in the upstream port. LRET Link Retrain.
Page 107 IDT Configuration Registers Notes Field Default Type Description Field Name Value SCLK HWINIT Slot Clock Configuration. When set, this bit indicates that the component uses the same physical reference clock that the platform provides. The initial value of this field is the state of the CCLKUS signal for the upstream port and the CCLKDS signal for downstream ports.
Page 108 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power sup- plied by the slot. A Set_Slot_Power_Limit message is generated using this field whenever this register is written or when the link transi- tions from a non DL_Up status to a DL_Up status.
Page 109 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSCE MRL Sensor Change Enable. This bit when set enables the generation of a Hot-Plug interrupt or wake-up event on a MRL sensor change event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP register.
Page 110 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.
Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Status. When an electrome- chanical interlock is implemented, this bit indicates the cur- rent status of the interlock. 0x0 - (disengaged) Electromechanical interlock disengaged 0x1 - (engaged) Electromechanical interlock engaged DLLLASC RW1C Data Link Layer Link Active State Change.
Page 112: Power Management Capability Structure
IDT Configuration Registers Notes PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) Field Default Type Description Field Name Value 31:0 Reserved Reserved field.
Page 113 IDT Configuration Registers Notes Field Default Type Description Field Name Value 24:22 AUXI AUX Current. This 3 bit field reports auxiliary current requirements by the function to retain PME Context when the main power rail is removed 0x0 - (self) Self Powered 0x1 - (55mA) Maximum current required is 55 mA 0x2 - (100mA) Maximum current required is 100 mA 0x3 - (160mA) Maximum current required is 160 mA...
Page 114: Message Signaled Interrupt Capability Structure
IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:13 DSCALE Data Scale. The optional data register is not imple- mented. PMES RW1C PME Status. This bit is set if a PME is generated by the FRSticky port even if the PMEE bit is cleared. This bit is not set when the bridge is propagating a PME message but the port is not itself generating a PME.
Page 115: Subsystem Id And Subsystem Vendor Id
IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction. The PES4T4 assumes that upstream and downstream ports generated MSIs are targeted to the root. Configuring the address contained in a port’s MSIADDR and MSIADDRU registers to an address that does not route to the root port and subsequently generating an MSI produces undefined...
Page 116: Extended Configuration Space Access Registers
IDT Configuration Registers Notes SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) Field Default Type Description Field Name Value 15:0 SSVID SubSystem Vendor ID. This field identifies the manufac- turer of the add-in card or subsystem. SSVID values are assigned by the PCI-SIG to insure unique- ness.
Page 117: Advanced Error Reporting (Aer) Enhanced Capability
IDT Configuration Registers Advanced Error Reporting (AER) Enhanced Capability Notes AERCAP - AER Capabilities (0x100) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x1 indicates an advanced error reporting capability structure. 19:16 CAPVER Capability Version. The value of 0x1. indicates compatibil- ity with version 1 of the specification.
Page 118 IDT Configuration Registers Notes AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specificiation. Reserved Reserved field. DLPERR Data Link Protocol Error Mask. When this bit is set, the Sticky corresponding bit in the AERUES register is masked.
Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Mask. When this bit is set, the corresponding bit in Sticky the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
Page 120 IDT Configuration Registers Notes Field Default Type Description Field Name Value UECOMP Unexpected Completion Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported error.
Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADVISO- RW1C Advisory Non-Fatal Error Status. This bit is set when an RYNF Sticky advisory non-fatal error is detected as described in Section 6.2.3.2.4 of the PCIe base 1.1 specification. 31:14 Reserved Reserved field.
Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRCGE ECRC Generation Enable. When this bit is set, ECRC gen- Sticky eration is enabled. ECRCCC ECRC Check Capable. This bit indicates if the device is capable of checking ECRC. ECRCCE ECRC Check Enable.
Page 123: Device Serial Number Enhanced Capability
IDT Configuration Registers Device Serial Number Enhanced Capability Notes SNUMCAP - Serial Number Capabilities (0x180) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x3 indicates a device serial number capability structure. 19:16 CAPVER Capability Version. The value of 0x1. indicates compatibil- ity with version 1 of the specification.
Page 124 IDT Configuration Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. LPEVCCNT Low Priority Extended VC Count. The value of 0x0 indi- cates only implementation of the default VC. Reserved Reserved field. REFCLK Reference Clock. Time-based WRR is not implemented. 11:10 PATBLSIZ Upstream:...
Page 125 IDT Configuration Registers Notes PVCCTL - Port VC Control (0x20C) Field Default Type Description Field Name Value LVCAT Load VC Arbitration Table. This bit, when set, updates the VC arbitration logic from the VC Arbitration Table for the VC resource. Since the device does not implement a VC arbitration table, this field has no functional effect.
Page 126 IDT Configuration Registers Notes Field Default Type Description Field Name Value 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field. 31:24 PATBLOFF Upstream: Port Arbitration Table Offset. This field contains the offset of the port arbitration table from the base address of the Vir- tual Channel Capability structure in double quad words (16 Downstream:...
Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value VCEN VC Enable. This field, when set, enables a virtual channel. Since the PES4T4 implements only a single VC, this field is hardwired to one (enabled). VCR0STS - VC Resource 0 Status (0x218) Field Default Type...
Page 128 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:24 PHASE6 Phase 6. This field contains the port ID for the corresponding port arbitration period. 31:28 PHASE7 Phase 7. This field contains the port ID for the corresponding port arbitration period.
Page 129: Power Budgeting Enhanced Capability
IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:24 PHASE22 Phase 22. This field contains the port ID for the correspond- ing port arbitration period. 31:28 PHASE23 Phase 23. This field contains the port ID for the correspond- ing port arbitration period.
Page 130 IDT Configuration Registers Notes PWRBDSEL - Power Budgeting Data Select (0x284) Field Default Type Description Field Name Value DVSEL Data Value Select. This field selects the Power Budgeting Data Value (PWRBDVx) register whose contents are reported in the Data (DATA) field of the Power Budgeting Data (PWRBD) register.
Page 131: Switch Control And Status Registers
IDT Configuration Registers Switch Control and Status Registers Notes SWSTS - Switch Status (0x328) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. These configuration pins determine the PES4T4 switch operating mode. 0x0 -Normal switch mode 0x1 -Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Reserved Reserved field.
Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except Sticky the SMBus interface remains in a reset state. When this bit is cleared, normal operation ensues. Setting or clearing this bit has no effect following a reset operation.
Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value WAKEDIR Wake Signal Direction. This bit field decides the direction of FRSticky the WAKEN signal. When the Vaux power is turned on, this bit field is set to 0x0. 0x0 - (input) WAKEN signal is an input 0x1 - (output) WAKEN signal is an output APWREN...
Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLP- MRL Automatic Power Off. When this bit is set and the Man- WROFF Sticky ual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automatically turned off when the MRL sensor indi- cates that the MRL is open.
Page 135 IDT Configuration Registers Notes GPIOFUNC - General Purpose I/O Control Function (0x338) Field Default Type Description Field Name Value 15:0 GPIOFUNC GPIO Function. Each bit in this field controls the corre- Sticky sponding GPIO pin. When set to a one, the corresponding GPIO pin operates as the alternate function as defined in Chapter 5, General Purpose Inputs/Outputs.
Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value NAERR RW1C No Acknowledge Error. This bit is set if an unexpected NACK is observed during a master SMBus transaction. The setting of this bit may indicate the following: that the addressed device does not exist on the SMBus (i.e., addressing error);...
Page 137 IDT Configuration Registers Notes EEPROMINTF - Serial EEPROM Interface (0x34C) Field Default Type Description Field Name Value 15:0 ADDR EEPROM Address. This field contains the byte address in the Serial EEPROM to be read or written. 23:16 DATA EEPROM Data. A write to this field will initiates a serial EEPROM read or write operation, as selected by the OP field, to the address specified in the ADDR field.
Page 138 IDT Configuration Registers Notes Field Default Type Description Field Name Value IOEXTM IO Expander Test Mode. Setting this bit puts the I/O expander interface into a test mode. In this test mode, I/O expander output signals generated by the PES4T4 core are ignored and values supplied to the I/O expander correspond to value written to the IOEDATA field.
Page 139 IDT Configuration Registers Notes IOEXPADDR1 - SMBus I/O Expander Address 1 (0x358) Field Default Type Description Field Name Value Reserved Reserved field. IOE4ADDR I/O Expander 4 Address. This field contains the SMBus Sticky address assigned to I/O expander 4 on the master SMBus interface.
Page 140: Internal Switch Error Control And Status Registers
IDT Configuration Registers Notes Field Default Type Description Field Name Value P2GPES Port 2 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal. This bit is never set if the cor- responding general purpose event is not enabled in the GPECTL register.
Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:16 Reserved Reserved field. SWERRSTS - Switch Internal Error Status (0x4D8) Field Default Type Description Field Name Value EEPE RW1C End-to-End Parity Error. This bit is set when an end-to-end parity error is detected at the port.
Page 142 IDT Configuration Registers Notes SWTOCTL - Switch Time-Out Control (0x4E4) Field Default Type Description Field Name Value Enable Switch Time-outs. When this bit is set, switch time- Sticky outs for this port are enabled. In this mode, a TLP will be dis- carded if it has been in this port’s input queue for more than the specified switch core time-out limit.
Page 143: Wakeup Protocol Registers
IDT Configuration Registers Notes SWTOCNT - Switch Time-Out Count (0x4EC) Field Default Type Description Field Name Value PTLPTOC Posted TLP Time-Out Count. This field is incremented Sticky each time a TLP is discarded from the port’s IPQ posted queue because of a time-out. This counter saturates at its maximum value.
Page 144 IDT Configuration Registers Notes PES4T4 User Manual 9 - 64 February 1, 2011...
Page 145: Jtag Boundary Scan
Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES4T4: AC-coupled and DC-coupled (also called AC and DC pins).
Page 146: Table 10.1 Jtag Pin Descriptions
IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.
Page 147: Boundary Scan Chain
IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PE4RN[0] PE4RP[0] PE4TN[0] PE4TP[0] PEREFCLKN — PEREFCLKP — SMBus MSMBCLK MSMBDAT General Purpose I/O GPIO[9,7,2:0] System Pins...
Page 148: Test Data Register (Dr)
IDT JTAG Boundary Scan Test Data Register (DR) Notes The Test Data register contains the following: Bypass register Boundary Scan registers Device ID register These registers are connected in parallel between a common serial input and a common serial data output and are described in the following sections.
Page 149: Figure 10.4 Diagram Of Output Cell
IDT JTAG Boundary Scan Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 10.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 10.5. shift_dr EXTEST Output enable from core...
Page 150: Instruction Register (Ir)
IDT JTAG Boundary Scan Instruction Register (IR) Notes The Instruction register allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both.
Page 151: Sample/Preload
IDT JTAG Boundary Scan SAMPLE/PRELOAD Notes The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary function of SAMPLE/PRELOAD is for sampling the system state at a particular moment.
Page 152: Validate
IDT JTAG Boundary Scan VALIDATE Notes The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std. 1149.1 specification. RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
Page 153 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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