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IDT Switch Partitions
Notes
PES48H12G2 User Manual
Hot Reset Mode Change Behavior
Modifying the operating mode of a port when the OMA field is set to hot reset has the following behavior
in addition to that specified by the common operating mode change behavior.
– All registers associated with the port are reset to their initial value except those designated Sticky
and SWSticky. Sticky and SWSticky register and field contents are preserved.
– If the previous operating mode is set to downstream switch port and the new operating mode is
also set to downstream switch port, then the LTSSM is directed to the hot reset state. Otherwise,
the LTSSM transitions to the Detect state.
Examples:
If the previous operating mode was upstream switch port and the new operating mode is upstream
switch port or unattached, the LTSSM transitions to the Detect state and does not transition to the
hot reset state.
If the previous operating mode was downstream switch port and the new operating mode is dis-
abled, then the LTSSM does not transition to the hot reset.
If the previous operating mode was disabled and the new operating mode is downstream switch
port, then the LTSSM transitions to L0 through the Detect state and does not transition to the hot
reset state.
Note that the Detect state on the link causes a hot reset on the downstream link partner.
In the above examples, if the LTSSM is unable to reach the L0 or hot reset states (e.g., due to an unpop-
ulated slot), then the LTSSM transitions to the Detect state. The port remains in a reset state for 250 µs
(i.e., two times T
). Following an exit from the hot reset state, if the new operating mode is an opera-
PERST
tional mode, then the link begins training from the Detect state in the specified LTSSM mode (i.e., upstream
or downstream).
Partition and Port Configuration
The configuration of partition states and port modes may be done statically or dynamically as described
below.
Static Reconfiguration
Static configuration requires a switch fundamental reset and is nothing more than configuration
performed either through modification of the sampled boot configuration vector or initialization performed
via serial EEPROM or SMBus during the fundamental reset sequence. Static configuration of partitions and
ports via the serial EEPROM is subject to the restrictions described in section Partition State Change via
EEPROM Loading on page 6-3 and section Port Operating Mode Change via EEPROM Loading on page 6-
8.
The following is a sample EEPROM sequence to configure two partitions. Partition 0 has one upstream
port (Port 0) and 2 downstream ports (Ports 1 to 2). Partition 1 has one upstream port (Port 3) and 2 down-
stream ports (Ports 4 and 5). Other ports are disabled. The sequence assumes the SWMODE signal in the
boot vector is set to 0xD (i.e., Multi-partition with serial EEPROM initialization). In this mode, all partitions
are initially disabled and all ports are initially unattached (see section Switch Mode Dependent Initialization
on page 5-6).
1. Set the following timer registers to a value of 0x0.
– Side Effect Delay Timer (SEDELAY register)
– Port Operating Mode Change Drain Delay Timer (POMCDELAY register)
– Reset Drain Delay Timer (RDRAINDELAY register)
– Upstream Secondary Bus Reset Delay (USSBRDELAY register)
2. Change the state of partition 0 to 'Active' by setting state field in the SWPART0CTL register.
3. Change the state of partition 1 to 'Active' by setting the state field in the SWPART1CTL register.
4. Add downstream ports to the partitions using the following sequence for each port.
6 - 15
April 5, 2013
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