Link Width Negotiation - Renesas IDT 89HPES48H12G2 User Manual

IDT Link Operation
Notes
PES48H12G2 User Manual
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES48H12G2
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
(a) x8 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES48H12G2
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
(c) x4 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES48H12G2
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
(e) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES48H12G2
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
(g) x1 Port without lane reversal
Figure 7.5 Merged Port Lane Reversal for Maximum Link Width of x8

Link Width Negotiation

The PES48H12G2 ports support the optional link variable width negotiation feature outlined in the PCI
Express 2.0 specification. The Maximum Link Width (MAXLNKWDTH) field in a port's PCI Express Link
Capabilities (PCIELCAP) register contains the maximum link width that the port can achieve. This field is of
RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of
this field allows the maximum link width of the port to be configured. The new link width takes effect the next
time full link training occurs.
lane 0
lane 1
lane 2
lane 3
PES48H12G2
lane 4
lane 5
lane 6
lane 7
lane 0
lane 1
lane 2
lane 3
PES48H12G2
lane 0
lane 1
PES48H12G2
lane 0
PES48H12G2
7 - 5
PExRP[0] lane 7
PExRP[1] lane 6
PExRP[2] lane 5
PExRP[3] lane 4
PExRP[4] lane 3
PExRP[5] lane 2
PExRP[6] lane 1
PExRP[7] lane 0
(b) x8 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4] lane 3
PExRP[5] lane 2
PExRP[6] lane 1
PExRP[7]
lane 0
(d) x4 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
lane 1
PExRP[6]
lane 0
PExRP[7]
(f) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
lane 0
PExRP[7]
(h) x1 Port with lane reversal
April 5, 2013