User Manuals: Renesas IDT 89HPES34H16G2 Express Switch

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Renesas IDT 89HPES34H16G2 Manual (317 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 4 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
4
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
7
Reference Documents
7
Table of Contents
11
PES34H16G2 Device Overview
25
Introduction
25
Features
25
Figure 2.1 PES34H16G2 Block Diagram
28
Logic Diagram
29
System Identification
30
Vendor ID
30
Device ID
30
Revision ID
30
Jtag ID
30
Ssid/Ssvid
30
Device Serial Number Enhanced Capability
30
PES34H16G2 Device Ids
30
Table 1.3 PES34H16G2 Revision ID
30
Pin Description
31
Table 1.4 PCI Express Interface Pins
31
Table 1.5 Reference Clock Pins
32
Table 1.6 Smbus Interface Pins
33
Table 1.7 General Purpose I/O Pins
33
Table 1.8 System Pins
36
Table 1.9 Test Pins
37
Table 1.10 Power, Ground, and Serdes Resistor Pins
38
Pin Characteristics
40
Table 1.11 Pin Characteristics
40
Architectural Overview
45
Introduction
45
Switch Partitioning
46
Figure 2.2 Transparent Pcie Switch
46
Figure 2.3 Partitionable PCI Express Switch
46
Dynamic Reconfiguration
47
Switch Core
49
Introduction
49
Switch Core Architecture
49
Ingress Buffer
49
Table 3.1 IFB Buffer Sizes
49
Egress Buffer
50
Table 3.2 EFB Buffer Sizes
50
Crossbar Interconnect
51
Datapaths
51
Table 3.3 Replay Buffer Storage Limit
51
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers
51
Packet Ordering
52
Arbitration
53
Table 3.4 Packet Ordering Rules in the PES34H16G2
53
Port Arbitration
54
Cut-Through Routing
54
Figure 3.2 Architectural Model of Arbitration
54
Table 3.5 Conditions for Cut-Through Transfers
55
Request Metering
56
Figure 3.3 Pcie Switch Static Rate Mismatch
57
Figure 3.4 Pcie Switch Static Rate Mismatch
57
Operation
58
Table 1.1 Table
58
Figure 3.5 Request Metering Count and Initial Value Loaded
58
Table 3.6 Request Metering Decrement Value
59
Figure 3.6 Decrement Value and Decrement Value Adjustment
59
Completion Size Estimation
60
Figure 3.7 Request Metering Counter Decrement Operation
60
Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation
60
Internal Errors
61
Switch Time-Outs
62
Memory SECDED ECC Protection
62
End-To-End Data Path Parity Protection
62
Clocking
65
Port Clocking Mode
65
Figure 4.1 Logical Representation of the PES34H16G2 Clocking Architecture
65
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State
66
Reset and Initialization
67
Introduction
67
Table 5.1 PES34H16G2 Reset Precedence
67
Boot Configuration Vector
68
Table 5.2 Boot Configuration Vector Signals
68
Switch Fundamental Reset
69
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization
71
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
71
Switch Mode Dependent Initialization
72
Table 5.3 Switch Mode Dependent Register Initialization
72
Port Merging
73
Partition Resets
74
Partition Fundamental Reset
74
Partition Hot Reset
75
Partition Upstream Secondary Bus Reset
75
Partition Downstream Secondary Bus Reset
76
Port Mode Change Reset
76
Switch Partitions
77
Introduction
77
Partition Configuration
77
Partition State
78
Figure 6.1 Allowable Partition State Transitions
78
Partition State Change
79
Switch Ports
80
Switch Port Mode
80
Port Operating Mode Change
83
Common Operating Mode Change Behavior
85
No Action Mode Change Behavior
90
Reset Mode Change Behavior
90
Hot Reset Mode Change Behavior
91
Partition and Port Configuration
91
Static Reconfiguration
91
Dynamic Reconfiguration
92
Link Operation
95
Introduction
95
Polarity Inversion
95
Lane Reversal
95
Figure 7.1 Unmerged Port Lane Reversal for Maximum Link Width of X4
96
Figure 7.2 Unmerged Port Lane Reversal for Maximum Link Width of X2
96
Figure 7.3 Merged Port Lane Reversal for Maximum Link Width of X2
97
Figure 7.4 Merged Port Lane Reversal for Maximum Link Width of X4
98
Link Width Negotiation
99
Figure 7.5 Merged Port Lane Reversal for Maximum Link Width of X8
99
Link Width Negotiation in the Presence of Bad Lanes
100
Dynamic Link Width Reconfiguration
100
Link Speed Negotiation
100
Link Speed Negotiation in the PES34H16G2
101
Software Management of Link Speed
102
Link Retraining
103
Link down
104
Slot Power Limit Support
104
Upstream Port
104
Downstream Port
104
Link States
105
Active State Power Management
105
Figure 7.6 PES34H16G2 ASPM Link Sate Transitions
105
L0S ASPM
106
L1 Aspm
106
L1 ASPM Entry Rejection Timer
107
Link Status
108
De-Emphasis Negotiation
108
Crosslink
109
Table 7.1 Crosslink Port Groups
109
Hot Reset Operation on a Crosslink
110
Link Disable Operation on a Crosslink
110
Gen1 Compatibility Mode
110
Table 7.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
111
Serdes
113
Introduction
113
Serdes Numbering and Port Association
113
Serdes Transmitter Controls
113
Driver Voltage Level and Amplitude Boost
113
De-Emphasis
114
Slew Rate
114
PCI Express Low-Swing Mode
114
Receiver Equalization
115
Programming of Serdes Controls
115
Programmable Voltage Margining and De-Emphasis
115
Serdes Transmitter Control Registers
116
Table 8.1 Serdes Transmit Level Controls in the S[X]Txlctl0 and S[X]Txlctl1 Registers
117
Table 8.2 Serdes Transmit Driver Settings in Gen1 Mode
118
Table 8.3 Serdes Transmit Driver Settings in Gen2 Mode with -3.5Db De-Emphasis
119
Table 8.4 Serdes Transmit Driver Settings in Gen2 Mode with -6.0Db De-Emphasis
120
Figure 8.1 De-Emphasis Applied on Link as a Function of the Fine De-Emphasis and Transmit
122
Figure 8.2 De-Emphasis Applied on Link as a Function of the Fine De-Emphasis and Transmit
122
Table 8.5 Transmitter Slew Rate Settings
123
Figure 8.3 De-Emphasis Applied on Link as a Function of the Fine De-Emphasis and Transmit
123
Transmit Margining Using the PCI Express Link Control 2 Register
124
Table 8.6 PCI Express Transmit Margining Levels Supported by the PES34H16G2
124
Low-Swing Transmitter Voltage Mode
125
Table 8.7 Serdes Transmit Drive Swing in Low Swing Mode at Gen1 Speed
125
Receiver Equalization Controls
126
Table 8.8 Serdes Transmit Drive Swing in Low Swing Mode at Gen2 Speed
126
Serdes Power Management
127
Theory of Operation
129
Introduction
129
Transaction Routing
129
Interrupts
129
Table 9.1 Switch Routing Methods
129
Downstream Port Interrupts
130
Legacy Interrupt Emulation
130
Table 9.2 Downstream Port Interrupts
130
Access Control Services
131
Table 9.3 Downstream to Upstream Port Interrupt Routing Based on Device Number
131
Figure 9.1 ACS Source Validation Example
132
Figure 9.2 ACS Peer-To-Peer Request Re-Direct at a Downstream Port
132
Table 9.4 Prioritization of ACS Checks for Request Tlps
133
Figure 9.3 ACS Upstream Forwarding Example
133
Error Detection and Handling
134
Table 9.5 Prioritization of ACS Checks for Completion Tlps
134
Table 9.6 TLP Types Affected by ACS Checks
134
Physical Layer Errors
135
Data Link Layer Errors
135
Table 9.7 Physical Layer Errors
135
Table 9.8 Data Link Layer Errors
135
Transaction Layer Errors
136
Table 9.9 Transaction Layer Errors Associated with the PCI-To-PCI Bridge Function
137
Table 9.10 Conditions Handled as Unsupported Requests (UR) by the PCI-To-PCI Bridge Function
139
Table 9.11 Ingress TLP Formation Checks Associated with the PCI-To-PCI Bridge Function
139
Table 9.12 Egress Malformed TLP Error Checks
140
Table 9.13 ACS Violations for Ports Operating in Downstream Switch Port Mode
141
Table 9.14 Prioritization of Transaction Layer Errors
142
Table 12.2 Table
143
Figure 9.4 Error Checking and Logging on a Received TLP
143
Routing Errors
144
Bus Locking
145
Hot-Plug and Hot-Swap
149
Introduction
149
Figure 10.1 Hot-Plug on Switch Downstream Slots Application
149
Figure 10.2 Hot-Plug with Switch on Add-In Card Application
150
Figure 10.3 Hot-Plug with Carrier Card Application
150
Hot-Plug Signals
151
Table 10.1 Port Hot Plug Signals
151
Table 10.2 Negated Value of Unused Hot-Plug Output Signals
152
Port Reset Outputs
153
Power Enable Controlled Reset Output
153
Figure 10.4 Power Enable Controlled Reset Output Mode Operation
153
Power Good Controlled Reset Output
154
Hot-Plug Events
154
Figure 10.5 Power Good Controlled Reset Output Mode Operation
154
Legacy System Hot-Plug Support
155
Hot-Swap
156
Figure 10.6 PES34H16G2 Hot-Plug Event Signalling
156
Notes
157
Power Management
157
Introduction
157
Table 11.1 PES34H16G2 Power Management State Transition Diagram
158
Figure 11.1 PES34H16G2 Power Management State Transition Diagram
158
PME Messages
159
PCI Express Power Management Fence Protocol
159
Upstream Switch Port or Downstream Switch Port Mode
159
Power Budgeting Capability
160
General Purpose I/O
161
Introduction
161
GPIO Configuration
161
Configured as an Input
161
Configured as an Output
161
Configured as an Alternate Function
161
Table 12.1 GPIO Pin Configuration
161
Smbus Interfaces
165
Introduction
165
Master Smbus Interface
165
Initialization
165
Figure 13.1 Split Smbus Interface Configuration
165
Serial EEPROM
166
Initialization from Serial EEPROM
166
Table 13.1 Serial EEPROM Smbus Address
166
Table 13.2 PES34H16G2 Compatible Serial Eeproms
166
Figure 13.2 Single Double Word Initialization Sequence Format
167
Figure 13.3 Sequential Double Word Initialization Sequence Format
168
Figure 13.4 Configuration Done Sequence Format
168
Programming the Serial EEPROM
169
Table 13.3 Serial EEPROM Initialization Errors
169
I/O Expanders
170
Table 13.4 I/O Expander Function Allocation
170
Table 13.5 I/O Expander Default Output Signal Value
171
Table 13.7 Pin Mapping I/O Expander 8
174
Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs
176
Table 13.11 I/O Expander 12 - Link up Status
177
Slave Smbus Interface
178
Initialization
178
Table 13.12 I/O Expander 13 - Link Activity Status
178
Table 13.13 Slave Smbus Address
178
Smbus Transactions
179
Table 13.14 Slave Smbus Command Code Fields
179
Figure 13.5 Slave Smbus Command Code Format
179
Table 13.15 CSR Register Read or Write Operation Byte Sequence
180
Figure 13.6 CSR Register Read or Write CMD Field Format
180
Table 13.16 CSR Register Read or Write CMD Field Description
181
Table 13.17 Serial EEPROM Read or Write Operation Byte Sequence
181
Table 13.18 Serial EEPROM Read or Write CMD Field Description
182
Figure 13.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
183
Figure 13.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
183
Figure 13.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
184
Figure 13.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
184
Figure 13.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
184
Multicast
185
Introduction
185
Addressing and Routing
185
Multicast TLP Determination
185
Figure 14.1 Multicast Group Address Ranges
186
Figure 14.2 Multicast Group Address Region Determination
187
Multicast TLP Routing
188
Multicast Egress Processing
188
Register Organization
191
Introduction
191
Table 15.1 Global Address Space Organization
191
Partial-Byte Access to Word and Dword Registers
192
Register Side-Effects
192
Address Maps
193
PCI-To-PCI Bridge Registers
193
Capability Structures
193
Table 15.2 Default PCI Capability List Linkage
194
Table 15.3 Default PCI Express Capability List Linkage
194
Figure 15.1 PCI-To-PCI Bridge Configuration Space Organization
195
Table 15.4 PCI-To-PCI Bridge Configuration Space Registers
196
IDT Proprietary Port Specific Registers
200
Figure 15.2 Proprietary Port Specific Register Organization
200
Table 15.5 Proprietary Port Specific Registers
201
Switch Configuration and Status Registers
202
Figure 15.3 Switch Configuration and Status Space Organization
202
Table 15.6 Switch Configuration and Status
203
PCI to PCI Bridge and Proprietary Port Specific Registers
209
Type 1 Configuration Header Registers
209
PCI Express Capability Structure
219
Power Management Capability Structure
235
Message Signaled Interrupt Capability Structure
237
Subsystem ID and Subsystem Vendor ID
239
Extended Configuration Space Access Registers
239
Advanced Error Reporting (AER) Enhanced Capability
240
Device Serial Number Enhanced Capability
249
PCI Express Virtual Channel Capability
250
Power Budgeting Enhanced Capability
255
ACS Extended Capability
257
Multicast Extended Capability
260
Proprietary Port Specific Registers
265
Port Control and Status Registers
265
Internal Error Control and Status Registers
267
Physical Layer Control and Status Registers
274
Power Management Control and Status Registers
277
Request Metering
277
Global Address Space Access Registers
279
Switch Configuration and Status Registers
281
Switch Control and Status Registers
281
Internal Switch Timer
283
Switch Partition and Port Registers
284
Protection
287
Serdes Control and Status Registers
287
General Purpose I/O Registers
295
Hot-Plug and Smbus Interface Registers
299
JTAG Boundary Scan
307
Introduction
307
Test Access Point
307
Signal Definitions
307
Figure 18.1 Diagram of the JTAG Logic
307
Table 18.1 JTAG Pin Descriptions
308
Figure 18.2 State Diagram of the TAP Controller
308
Boundary Scan Chain
309
Table 18.2 Boundary Scan Chain
309
Test Data Register (DR)
312
Boundary Scan Registers
312
Figure 18.3 Diagram of Observe-Only Input Cell
312
Figure 18.4 Diagram of Output Cell
313
Figure 18.5 Diagram of Bidirectional Cell
313
Instruction Register (IR)
314
Extest
314
Table 18.3 Instructions Supported by the JTAG Boundary Scan
314
Sample/Preload
315
Bypass
315
Clamp
315
Idcode
315
Table 18.4 System Controller Device Identification Register
315
Figure 18.6 Device ID Register Format
315
Validate
316
Extest_Train
316
Extest_Pulse
316
Reserved
316
Usage Considerations
316

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User Manuals: Renesas IDT 89HPES34H16G2 Express Switch

Renesas IDT 89HPES34H16G2 Manual (317 pages)

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