Renesas IDT 89HPES4T4G2 Manuals

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Renesas IDT 89HPES4T4G2 User Manual (161 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 2 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
9
PES4T4G2 Device Overview
21
Introduction
21
Features
21
Table 1.1 Table
23
Logic Diagram - PES4T4G2
24
Vendor ID
25
Device ID
25
Revision ID
25
Jtag ID
25
Ssid/Ssvid
25
PES4T4G2 Device ID
25
Pin Description
26
Table 1.3 PCI Express Interface Pins
26
Table 1.4 Smbus Interface Pins
26
Table 1.5 General Purpose I/O Pins
27
Table 1.6 System Pins
28
Table 1.7 Test Pins
28
Table 1.8 Power, Ground, and Serdes Resistor Pins
29
Pin Characteristics
30
Table 1.9 Pin Characteristics
30
Clocking, Reset and Initialization
33
Clocking
33
Table 2.1 Boot Configuration Vector Signals
33
Reset
34
Fundamental Reset
34
Figure 2.1 Fundamental Reset with Serial EEPROM Initialization
35
Hot Reset
36
Upstream Secondary Bus Reset
36
Downstream Secondary Bus Reset
37
Downstream Port Reset Outputs
37
Power Enable Controlled Reset Output
38
Power Good Controlled Reset Output
38
Figure 2.2 Power Enable Controlled Reset Output Mode Operation
38
Figure 2.3 Power Good Controlled Reset Output Mode Operation
38
Link Operation
41
Introduction
41
Polarity Inversion
41
Link Speed Negotiation
41
Link Speed Negotiation in the PES4T4G2
42
Software Management of Link Speed
42
Link Reliability
43
Autonomous Link Reliability Management
43
Link Retraining
44
Link down
45
Slot Power Limit Support
45
Upstream Port
45
Link States
46
Active State Power Management
46
Figure 3.1 PES4T4G2 ASPM Link Sate Transitions
46
Link Status
47
De-Emphasis Negotiation
47
Low-Swing Transmitter Voltage Mode
48
Crosslink
48
General Purpose I/O
49
Introduction
49
GPIO Configuration
49
GPIO Pin Configured as an Input
49
Table 4.1 General Purpose I/O Pin Alternate Function
49
Table 4.2 GPIO Pin Configuration
49
GPIO Pin Configured as an Output
50
GPIO Pin Configured as an Alternate Function
50
Smbus Interfaces
51
Introduction
51
Figure 5.1 Smbus Interface Configuration Examples
51
Master Smbus Interface
52
Initialization
52
Serial EEPROM
52
Table 5.1 PES4T4G2 Compatible Serial Eeproms
52
Figure 5.2 Single Double Word Initialization Sequence Format
53
Figure 5.3 Sequential Double Word Initialization Sequence Format
54
Figure 5.4 Configuration Done Sequence Format
54
Table 5.2 Serial EEPROM Initialization Errors
55
I/O Expanders
56
Table 5.3 I/O Expander Function Allocation
56
Table 5.4 I/O Expander Default Output Signal Value
57
Table 5.5 I/O Expander 0 Signals
60
Table 5.6 I/O Expander 1 Signals
60
Table 5.7 I/O Expander 2 Signals
62
Table 5.8 I/O Expander 3 Signals
62
Slave Smbus Interface
63
Table 5.9 I/O Expander 4 Signals
63
Initialization
64
Smbus Transactions
64
Table 5.10 Slave Smbus Command Code Fields
64
Figure 5.5 Slave Smbus Command Code Format
64
Table 5.11 CSR Register Read or Write Operation Byte Sequence
65
Table 5.12 CSR Register Read or Write CMD Field Description
65
Figure 5.6 CSR Register Read or Write CMD Field Format
65
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence
66
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
66
Table 5.14 Serial EEPROM Read or Write CMD Field Description
67
Figure 5.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
67
Figure 5.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
68
Figure 5.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
68
Figure 5.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
68
Figure 5.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
68
Figure 5.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
69
Power Management
71
Introduction
71
Figure 6.1 PES4T4G2 Power Management State Transition Diagram
71
PME Messages
72
PCI-Express Power Management Fence Protocol
72
Table 6.1 PES4T4G2 Power Management State Transition Diagram
72
Power Budgeting Capability
73
Hot-Plug and Hot-Swap
75
Hot-Plug
75
Figure 7.1 Hot-Plug on Switch Downstream Slots Application
75
Figure 7.2 Hot-Plug with Switch on Add-In Card Application
76
Figure 7.3 Hot-Plug with Carrier Card Application
76
Hot-Plug I/O Expander
78
Hot-Plug Interrupts and Wake-Up
78
Legacy System Hot-Plug Support
79
Hot-Swap
80
Figure 7.4 PES4T4G2 Hot-Plug Event Signalling
80
Configuration Registers
81
Configuration Space Organization
81
Table 8.1 Base Addresses for Port Configuration Space Register
81
Upstream Port (Port 0)
82
Table 8.2 Upstream Port 0 Configuration Space Registers
82
Figure 8.1 Port Configuration Space Organization
82
Downstream Ports
86
Table 8.3 Downstream Ports 1 through 5 Configuration Space Registers
86
Register Definitions
90
Type 1 Configuration Header Registers
90
PCI Express Capability Structure
100
Power Management Capability Structure
116
Message Signaled Interrupt Capability Structure
117
Subsystem ID and Subsystem Vendor ID
119
Extended Configuration Space Access Registers
119
Advanced Error Reporting (AER) Enhanced Capability
120
Device Serial Number Enhanced Capability
128
PCI Express Virtual Channel Capability
129
Power Budgeting Enhanced Capability
135
Switch Control and Status Registers
136
Autonomous Link Reliability Management
149
JTAG Boundary Scan
153
Introduction
153
Test Access Point
153
Signal Definitions
153
Figure 9.1 Diagram of the JTAG Logic
153
Table 9.1 JTAG Pin Descriptions
154
Figure 9.2 State Diagram of Pes4T4G2'S TAP Controller
154
Boundary Scan Chain
155
Table 9.2 Boundary Scan Chain
155
Test Data Register (DR)
156
Boundary Scan Registers
156
Figure 9.3 Diagram of Observe-Only Input Cell
156
Figure 9.4 Diagram of Output Cell
157
Figure 9.5 Diagram of Bidirectional Cell
157
Instruction Register (IR)
158
Extest
158
Table 9.3 Instructions Supported by Pes4T4G2'S JTAG Boundary Scan
158
Sample/Preload
159
Bypass
159
Clamp
159
Idcode
159
Table 9.4 System Controller Device Identification Register
159
Figure 9.6 Device ID Register Format
159
Validate
160
Reserved
160
Usage Considerations
160

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