Page 1 ® 89HPES4T4G2 ™ PCI Express® Switch User Manual May 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: About This Manual
About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES4T4G2, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
Page 4: Numeric Representations
Notes Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These terms are illustrated in Figure 1. single clock cycle high-to-low transition low-to-high...
Page 5: Register Terminology
Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCIe root configura- tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial- ization.
Page 6: Use Of Hypertext
Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.
Page 7 Notes March 30, 2009: In Chapter 5, deleted old Tables 5.1 and 5.11 dealing with master and slave SMBus addresses. May 7, 2009: In Chapter 3, revised the Lane Reversal section. July 21, 2009: In Chapter 3, revised section Dynamic Link Width Reconfiguration Support in the PES4T4G2.
Page 8 Notes PES4T4G2 User Manual May 23, 2013...
Page 9: Table Of Contents
Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
Page 10 IDT Table of Contents Notes Downstream Port........................3-5 Link States ............................3-6 Active State Power Management ....................3-6 Link Status ............................3-7 De-emphasis Negotiation ....................... 3-7 Low-Swing Transmitter Voltage Mode.................... 3-8 Crosslink ............................3-8 General Purpose I/O Introduction ............................. 4-1 GPIO Configuration ........................
Page 11 IDT Table of Contents Notes Power Budgeting Enhanced Capability ................8-55 Switch Control and Status Registers ..................8-56 Autonomous Link Reliability Management ................8-69 JTAG Boundary Scan Introduction ............................. 9-1 Test Access Point ........................... 9-1 Signal Definitions ..........................9-1 Boundary Scan Chain........................9-3 Test Data Register (DR) .........................
Page 12 IDT Table of Contents Notes PES4T4G2 User Manual May 23, 2013...
Page 13 List of Tables ® Table 1.1 PES4T4G2 Device ID ......................1-4 Notes Table 1.2 PES4T4G2 Revision ID ....................... 1-4 Table 1.3 PCI Express Interface Pins....................1-5 Table 1.4 SMBus Interface Pins ......................1-5 Table 1.5 General Purpose I/O Pins....................1-6 Table 1.6 System Pins.........................1-7 Table 1.7...
Page 14 IDT List of Tables Notes PES4T4G2 User Manual May 23, 2013...
Page 15 List of Figures ® Figure 1.1 PES4T4G2 Architectural Block Diagram ................1-2 Notes Figure 1.2 PES4T4G2 Logic Diagram ....................1-3 Figure 2.1 Fundamental Reset with Serial EEPROM initialization ............2-3 Figure 2.2 Power Enable Controlled Reset Output Mode Operation ..........2-6 Figure 2.3 Power Good Controlled Reset Output Mode Operation .............2-6 Figure 3.1 PES4T4G2 ASPM Link Sate Transitions ................3-6 Figure 5.1...
Page 16 IDT List of Figures Notes PES4T4G2 User Manual viii May 23, 2013...
Page 17 Register List ® AERCAP - AER Capabilities (0x100) ..................... 8-40 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 8-46 AERCES - AER Correctable Error Status (0x110) ................. 8-45 AERCTL - AER Control (0x118)......................8-47 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............8-47 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
Page 18 IDT Register List Notes PBUSN - Primary Bus Number Register (0x018)..................8-14 PCICMD - PCI Command Register (0x004)....................8-10 PCIECAP - PCI Express Capability (0x040) ...................8-20 PCIEDCAP - PCI Express Device Capabilities (0x044) ................8-21 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............8-32 PCIEDCTL - PCI Express Device Control (0x048)..................8-22 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................8-33 PCIEDSTS - PCI Express Device Status (0x04A) ..................8-23...
Page 19 IDT Register List Notes SUBUSN - Subordinate Bus Number Register (0x01A)................8-14 SWCTL - Switch Control (0x404) ......................8-57 SWSTS - Switch Status (0x400) ......................8-56 VCR0CAP- VC Resource 0 Capability (0x210)..................8-51 VCR0CTL- VC Resource 0 Control (0x214)....................8-51 VCR0STS - VC Resource 0 Status (0x218)....................8-52 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............8-53 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............8-53 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............8-54...
Page 20 IDT Register List Notes PES4T4G2 User Manual May 23, 2013...
Page 21: Pes4T4G2 Device Overview
Chapter 1 PES4T4G2 Device Overview ® Introduction Notes The 89HPES4T4G2, a 4-lane 4-port Gen2 PCI Express® switch, is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES4T4G2 is a peripheral chip that performs PCI Express base switching with a feature set optimized for servers, storage, communications, and consumer applica- tions.
Page 22 IDT PES4T4G2 Device Overview • Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 – Supports PCI Express Power Budgeting Capability – Configurable SerDes power consumption • Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode • Supports numerous SerDes Transmit Voltage Margin settings –...
Page 23: Table 1.1 Table
IDT PES4T4G2 Device Overview Switch Core D-Bus Bus Decoupler D-Bus U-Bus Arbiter Queue U-Bus Arbiter GPIO Controller Master SMBus Interface Slave Input Input Input Input Input Input SMBus Frame Frame Frame Frame Frame Frame Interface Buffer Buffer Buffer Buffer Buffer Buffer Reset Controller...
Page 24: Logic Diagram - Pes4T4G2
IDT PES4T4G2 Device Overview Logic Diagram — PES4T4G2 Notes Reference PEREFCLKP Clocks PEREFCLKN PCI Express PCI Express PE0TP[0] PE0RP[0] Switch Switch PE0TN[0] PE0RN[0] SerDes Output SerDes Input Port 0 Port 0 PCI Express PCI Express PE1TP[0] PE1RP[0] Switch Switch PE1TN[0] PE1RN[0] SerDes Output SerDes Input...
Page 25: Vendor Id
IDT PES4T4G2 Device Overview Vendor ID Notes All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES4T4G2 device ID is shown in Table 1.1. PCIe Device Device ID 0x806C Table 1.1 PES4T4G2 Device ID Revision ID...
Page 26: Pin Description
IDT PES4T4G2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES4T4G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
Page 27: Table 1.5 General Purpose I/O Pins
IDT PES4T4G2 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. GPIO[1] General Purpose I/O.
Page 28: Table 1.6 System Pins
IDT PES4T4G2 Device Overview Notes Signal Type Name/Description CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.
Page 29: Table 1.8 Power, Ground, And Serdes Resistor Pins
IDT PES4T4G2 Device Overview Notes Signal Type Name/Description REFRES0 Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES1 Port 1 External Reference Resistor.
Page 30: Pin Characteristics
IDT PES4T4G2 Device Overview Pin Characteristics Notes Note: Some input pads of the PES4T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Page 31 IDT PES4T4G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor SerDes Refer- REFRES0 Analog Input ence Resistors REFRES1 REFRES2 REFRES3 Table 1.9 Pin Characteristics (Part 2 of 2) Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. All receiver pins set the DC common mode voltage to ground.
Page 32 IDT PES4T4G2 Device Overview Notes PES4T4G2 User Manual 1 - 12 May 23, 2013...
Page 33: Clocking, Reset And Initialization
Chapter 2 Clocking, Reset and Initialization ® Clocking Notes The PES4T4G2 has a single differential reference clock input (PEREFCLKP/PEREFCLKN) that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. The frequency of the reference clock input is set to 100MHz.
Page 34: Reset
IDT Clocking, Reset and Initialization Reset Notes The PES4T4G2 defines four Conventional Reset categories: Fundamental reset, Hot Reset, Upstream Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset. – A Fundamental Reset causes all logic in the PES4T4G2 to be returned to an initial state. –...
Page 35: Figure 2.1 Fundamental Reset With Serial Eeprom Initialization
IDT Clocking, Reset and Initialization Notes • If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the current link parameters.
Page 36: Hot Reset
IDT Clocking, Reset and Initialization Hot Reset Notes A hot reset may be initiated by any of the following conditions: – Reception of TS1 ordered-sets on the upstream port indicating a hot reset. – Data link layer of the upstream port transitions to the DL_Down state. –...
Page 37: Downstream Secondary Bus Reset
IDT Clocking, Reset and Initialization Notes When an Upstream Secondary Bus Reset occurs, the following sequence is executed. 1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set. 2.
Page 38: Power Enable Controlled Reset Output
IDT Clocking, Reset and Initialization Notes Downstream port reset outputs can be configured to operate in one of two modes. These modes are power enable controlled reset output and power good controlled reset output. The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control (HPCFGCTL) register.
Page 39 IDT Clocking, Reset and Initialization Notes When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power (RST2PWR) field in the HPCFGCTL register.
Page 40 IDT Clocking, Reset and Initialization Notes PES4T4G2 User Manual 2 - 8 May 23, 2013...
Page 41: Link Operation
Chapter 3 Link Operation ® Introduction Notes Link operation in the PES4T4G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 Gbps and 5.0 Gbps. The PES4T4G2 contains six x4 ports which may be merged in pairs to form x8 ports.
Page 42: Link Speed Negotiation In The Pes4T4G2
IDT Link Operation Link Speed Negotiation in the PES4T4G2 Notes The PES4T4G2 ports support per lane data rates of 5.0 Gbps and 2.5 Gbps. The highest data rate of each link is determined dynamically, and depends on the following factors: –...
Page 43: Link Reliability
IDT Link Operation Notes Speed (CLS) field of the port’s Link Status Register (PCIELSTS). Note that to force link speed to a value other than the default value, the TLS field could be configured through Serial EEPROM initialization and full link retraining forced.
Page 44: Link Retraining
IDT Link Operation Notes As mentioned above, when the rate of errors crosses an specified threshold, the Phy’s LTSSM down- grades the link speed. The threshold is programmed via the Autonomous Link Reliability Error Rate Threshold (ALRERT) register. This register contains two fields: Error Threshold (ERRT) and Monitoring Period (PERIOD).
Page 45: Link Down
IDT Link Operation Notes Writing a one to the Link Retrain (LRET) bit in a downstream port’s PCI Express Link Control (PCIELCTL) register regardless of the REGUNLOCK bit state in the SWCTL register forces the down- stream PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Recovery state. Writing a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTSE 0) register of any port forces that port’s PCIe link to retrain.
Page 46: Link States
IDT Link Operation Link States Notes The PES4T4G2 supports the following link states – L0 • Fully operational link state – L0s • Automatically entered low power state with shortest exit latency – L1 • Lower power state than L0s •...
Page 47: Link Status
IDT Link Operation Notes The upstream switch port has the following L0s entry conditions. – The receive lanes of all of the switch downstream ports which are not in a low power state (i.e., D3) and whose link is not down are in the L0s state. –...
Page 48: Low-Swing Transmitter Voltage Mode
IDT Link Operation Low-Swing Transmitter Voltage Mode Notes The PES4T4G2 ports support the optional low-swing transmit voltage mode defined in the PCIe 2.0 specification. In this mode, the transmitter’s voltage level is set to approximately half the value of the full- swing (default) mode.
Page 49: General Purpose I/O
Chapter 4 General Purpose I/O ® Introduction Notes The PES4T4G2 has 7 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions.GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.
Page 50: Gpio Pin Configured As An Output
IDT General Purpose I/O GPIO Pin Configured as an Output Notes When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the value in the corresponding bit position of the GPIOD register is driven on the pin. System designers should treat the GPIO outputs as asynchronous outputs.
Page 51: Smbus Interfaces
Chapter 5 SMBus Interfaces ® Introduction Notes The PES4T4G2 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES4T4G2, allowing every register in the device to be read or written by an external SMBus master.
Page 52: Master Smbus Interface
IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.
Page 53: Figure 5.2 Single Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes A blank serial EEPROM contains 0xFF in all data bytes. Therefore, when the PES4T4G2 is configured to initialize from serial EEPROM and the second byte read from the EEPROM is0xFF, loading of the serial EEPROM is aborted, the computed checksum is ignored, and normal device operation beings (i.e., the device operates in the same manner as though i were not configured to initialize from the serial EEPROM).
Page 54: Figure 5.3 Sequential Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 5.3 Sequential Double Word Initialization Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end...
Page 55: Table 5.2 Serial Eeprom Initialization Errors
IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence. The correct result should always be 0xFF (i.e., all ones).
Page 56: I/O Expanders
IDT SMBus Interfaces I/O Expanders Notes The PES4T4G2 utilizes external SMBus/I C-bus I/O expanders connected to the master SMBus inter- face for hot-plug and port status signals. The PES4T4G2 is designed to work with Phillips PCA9555 compatible I/O expanders (i.e., PCA9555, PCA9535, and PCA9539). See the Phillips PCA9555 data sheet for details on the operation of this device.
Page 57: Table 5.4 I/O Expander Default Output Signal Value
IDT SMBus Interfaces Notes SMBus I/O Default Expander Signal Description Value (I/O-x.4) P2AIN Attention indicator output (off) (I/O-x.5) P2PIN Power indicator output (on) (I/O-x.6) P2PEP Power enable output (on) (I/O-x.7) P2ILOCKP Electromechanical interlock (negated - off) Table 5.4 I/O Expander Default Output Signal Value The following I/O expander configuration sequence is issued by the PES4T4G2 to I/O expanders zero, one and three (i.e., the ones that contain hot-plug signals).
Page 58 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES4T4G2 to I/O expander four (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
Page 59 IDT SMBus Interfaces Notes Regardless of the state of the interrupt output of the I/O expander, the PES4T4G2 will not issue a master SMBus transaction to read the updated state of the I/O expander inputs more frequently than once every 40 milliseconds (i.e., the I/O expander update period). This delay in sampling may be used to elimi- nate external debounce circuitry.
Page 60: Table 5.5 I/O Expander 0 Signals
IDT SMBus Interfaces Notes I/O Expander 0 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P2APN Port 2 attention push button input 1 (I/O-0.1) P2PDN Port 2 presence detect input 2 (I/O-0.2) P2PFN Port 2 power fault input 3 (I/O-0.3) P2MRLN Port 2 manually-operated retention latch (MRL) input 4 (I/O-0.4)
Page 61 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) Unused 12 (I/O-1.4) Unused 13 (I/O-1.5) Unused 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused Table 5.6 I/O Expander 1 Signals I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y. PES4T4G2 User Manual 5 - 11 May 23, 2013...
Page 62: Table 5.7 I/O Expander 2 Signals
IDT SMBus Interfaces Notes I/O Expander 2 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) Unused 1 (I/O-0.1) Unused 2 (I/O-0.2) Unused 3 (I/O-0.3) Unused 4 (I/O-0.4) Unused 5 (I/O-0.5) Unused 6 (I/O-0.6) Unused 7 (I/O-0.7) Unused 8 (I/O-1.0) Unused 9 (I/O-1.1) P1PWRGDN Port 1 power good input...
Page 63: Slave Smbus Interface
IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) P1MRLN Port 1 manually-operated retention latch (MRL) input 12 (I/O-1.4) P1AIN Port 1 attention indicator output 13 (I/O-1.5) P1PIN Port 1 power indicator output 14 (I/O-1.6) P1PEP Port 1 power enable output 15 (I/O-1.7) P1ILOCKP Port 1 electromechanical interlock...
Page 64: Initialization
IDT SMBus Interfaces Initialization Notes Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-2). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The address specified by the SSMBADDR[5,3:1] signals is hardwired to 0x77. SMBus Transactions The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master (see the SMBus 2.0 specification for a detailed description of these transactions):...
Page 65: Table 5.11 Csr Register Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes CSR Register Read or Write Operation Table 5.11 indicates the sequence of data as it is presented on the slave SMBus following the byte address of the Slave SMBus interface. Byte Field Position Name Description CCODE Command Code.
Page 66: Table 5.13 Serial Eeprom Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes Name Type Description Field BEUU Read/Write Byte Enable Upper. When set, the byte enable for bits [31:24] of the data word is enabled. Read/Write CSR Operation. This field encodes the CSR operation to be performed. 0 - CSR write 1 - CSR read Reserved.
Page 67: Table 5.14 Serial Eeprom Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Name Type Description Field Serial EEPROM Operation. This field encodes the serial EEPROM oper- ation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address. When this bit is set the serial EEPROM SMBus address specified in the EEADDR is used instead of that specified in the ADDR field in the EEPROMINTF register.
Page 68: Figure 5.9 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec
IDT SMBus Interfaces Notes PES4T4G2 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES4T4G2 Slave CCODE (PES4T4G2 not ready with data) SMBus Address START,END PES4T4G2 Slave CCODE PES4T4G2 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address ADDRL ADDRU DATA...
Page 69: Figure 5.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled
IDT SMBus Interfaces Notes PES4T4G2 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES4T4G2 Slave CCODE ADDRU SMBus Address END, Byte PES4T4G2 Slave CCODE (PES4T4G2 not ready with data) SMBus Address START,Word PES4T4G2 Slave CCODE SMBus Address START,Word PES4T4G2 Slave CMD (status) ADDRL SMBus Address...
Page 70 IDT SMBus Interfaces Notes PES4T4G2 User Manual 5 - 20 May 23, 2013...
Page 71: Power Management
Chapter 6 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES4T4G2 is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.
Page 72: Pme Messages
IDT Power Management Notes From State To State Description D0 Uninitialized Power-on Fundamental Reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Man- agement Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.
Page 73: Power Budgeting Capability
IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES4T4G2 receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES4T4G2 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
Page 74 IDT Power Management Notes PES4T4G2 User Manual 6 - 4 May 23, 2013...
Page 75: Hot-Plug And Hot-Swap
Chapter 7 Hot-Plug and Hot-Swap ® Hot-Plug Notes As illustrated in Figures 7.1 through 7.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 7.1 illustrates the use of the PES4T4G2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
Page 76: Figure 7.2 Hot-Plug With Switch On Add-In Card Application
IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES4T4G2 Port x Port y PCI Express PCI Express Device Device Figure 7.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES4T4G2 Master SMBus Port x Port y SMBus I/O...
Page 77 IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES4T4G2 in an application in which one or more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a downstream slot.
Page 78: Hot-Plug I/O Expander
IDT Hot-Plug and Hot-Swap Notes ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the corresponding PxILOCKP I/O expander signal output. When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open.
Page 79: Legacy System Hot-Plug Support
IDT Hot-Plug and Hot-Swap Legacy System Hot-Plug Support Notes Some systems require support for operating systems that lack PCIe hot-plug support. The PES4T4G2 supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot- plug.
Page 80: Hot-Swap
IDT Hot-Plug and Hot-Swap Notes General Purpose Event Enable General Purpose Event Mechanism Interrupt Slot Control Disable Register Activate INTx Hot-Plug Interrupt Mechanism Enable Slot Status Register Activate MSI Mechanism Command Completed Enable Command Completed MSI Enable RW1C RW1C Attention Button Pressed Enable Attention Button Pressed...
Page 81: Configuration Registers
Chapter 8 Configuration Registers Configuration Space Organization Notes Each software visible register in the PES4T4G2 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES4T4G2 that cannot be accessed by the root. Each software visible register in the PES4T4G2 has a system address.
Page 82: Upstream Port (Port 0)
IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting Enhanced Capability 0x400 Switch Control...
Page 83 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 8-13 0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13 0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13 0x014 DWord P0_BAR1...
Page 84 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 8-33 0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 8-33 0x070 Word P0_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 8-33...
Page 85 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8- 0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) on page 8-49 0x204 DWord P0_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 8-49...
Page 86: Downstream Ports
IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 8-57 0x408 DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 8-59 0x418 DWord GPIOFUNC GPIOFUNC - General Purpose I/O Control Function (0x418) on page 8-61 0x41C DWord...
Page 87 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 8-13 0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13 0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 8-13 0x00F Byte Px_BIST...
Page 88 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x054 DWord Px_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page 8-28 0x058 Word Px_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 8-30 0x05A Word Px_PCIESSTS PCIESSTS - PCI Express Slot Status (0x05A) on page 8-31 0x064 DWord...
Page 89 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword Px_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 8- 0x120 Dword Px_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 8- 0x124 Dword Px_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 8-...
Page 90: Register Definitions
IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x31C Dword Px_PWRBDV7 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 8-56 0x500 Dword Px_SERDESCTL SERDESCTL- SerDes Control (0x500) on page 8-66 0x530 Dword Px_PHYLCFG0 PHYLCFG0 - Phy Link Configuration 0 (0x530) on page 8-67 0x538 Dword...
Page 91 IDT Configuration Registers Notes Field Default Type Description Field Name Value Memory Access Enable. When this bit is cleared, the bridge does not respond to memory and prefetchable memory space access from the primary bus specified by MBASE, MLIMIT, PMBASE and PMLIMIT. 0x0 - (disable) Disable memory space.
Page 92 IDT Configuration Registers Notes Field Default Type Description Field Name Value INTS INTx Status. This bit is set when an INTx interrupt is pending from the device. INTx emulation interrupts forwarded by switch ports from devices downstream of the bridge are not reflected in this bit. For downstream ports, this bit is set if an interrupt has been “asserted”...
Page 93 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 0x04 Sub Class Code. This value indicates that the device is a PCI- PCI bridge. 23:16 BASE 0x06 Base Class Code. This value indicates that the device is a bridge.
Page 94 IDT Configuration Registers Notes BAR1 - Base Address Register 1 (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus num- ber of the PCI bus segment to which the primary interface of the bridge is connected.
Page 95 IDT Configuration Registers Notes IOBASE - I/O Base Register (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. 0x0 - (io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing. Reserved Reserved field.
Page 96 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Detected Parity Error. This bit is set by the bridge whenever it receives a poisoned TLP on the secondary side regardless of the state of the PERRE bit in the PCI Command register MBASE - Memory Base Register (0x020) Field Default...
Page 97 IDT Configuration Registers Notes PMLIMIT - Prefetchable Memory Limit Register (0x026) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge sup- ports 32-bit or 64-bit prefetchable memory addressing. This bit always reflects the value in the PMCAP field in the PMBASE reg- ister.
Page 98 IDT Configuration Registers Notes IOLIMITU - I/O Limit Upper Register (0x032) Field Default Type Description Field Name Value 15:0 IOLIMITU Prefetchable IO Limit Upper. This field specifies the upper 16- bits of IOLIMIT. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
Page 99 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot- plug by the downstream ports and to report memory errors by the upstream port.
Page 100: Pci Express Capability Structure
IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
Page 101 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD HWINIT Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. For all bond options the default value is 0x4 which corresponds to 2048 bytes.
Page 102 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:26 CSPLS Captured Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for the upstream port.
Page 103 IDT Configuration Registers Notes Field Default Type Description Field Name Value PFEN Phantom Function Enable. The bridge does not support phan- tom function numbers. Therefore, this field is hardwired to zero. AUXPMEN Auxiliary Power PM Enable. The device does not implement this capability.
Page 104 IDT Configuration Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. This field indicates the supported link speeds of the port. 1 - (gen1) 2.5 Gbps 2 - (gen2) 5 Gbps others - reserved The initial value of this field is always 0x2 for the upstream and downstream ports.
Page 105 IDT Configuration Registers Notes Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indi- cates support for the link bandwidth notification status and inter- rupt mechanisms. The PES4T4G2 downstream ports support the Downstream: capability.
Page 106 IDT Configuration Registers Notes Field Default Type Description Field Name Value LRET Link Retrain. Writing a one to this field initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. This field always returns zero when read. It is permitted to set this bit while simultaneously modifying other fields in this register.
Page 107 IDT Configuration Registers Notes Field Default Type Description Field Name Value LABWINTEN Link Autonomous Bandwidth Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the LABWSTS bit has been set in the PCIELSTS register. If the LBN field in the PCIELCAP register is cleared, this field is hardwired to zero.
Page 108 IDT Configuration Registers Notes Field Default Type Description Field Name Value SCLK HWINIT Slot Clock Configuration. When set, this bit indicates that the component uses the same physical reference clock that the plat- form provides. The initial value of this field is the state of the CCLKUS signal for the upstream port and the CCLKDS signal for downstream ports.
Page 109 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLP MRL Sensor Present. This bit is set when an MRL Sensor is implemented for the port. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
Page 110 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:19 PSLOTNUM Physical Slot Number. This field indicates the physical slot num- ber attached to this port. For devices interconnected on the sys- tem board, this field should be initialized to zero. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value Attention Indicator Control. When read, this register returns the current state of the Attention Indicator. Writing to this register sets the indicator. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP register.
Page 112 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSC RW1C MRL Sensor Changed. Set when an MRL Sensor state change is detected. RW1C Presence Detected Changed. Set when a Presence Detected change is detected. RW1C Command Completed. This bit is set when the Hot-Plug Con- troller completes an issued command.
Page 113 IDT Configuration Registers Notes PCIEDCTL2 - PCI Express Device Control 2 (0x068) Field Default Type Description Field Name Value Reserved Reserved field. ARIFEN ARI Forwarding Enable. When set, the downstream port dis- ables its traditional Device Number field being zero enforcement when turning a Type 1 configuration request into a Type 0 config- uration request, permitting access to the Extended Functions in an ARI device immediately below the port.
Page 114 IDT Configuration Registers Notes Field Default Type Description Field Name Value HASD Hardware Autonomous Speed Disable. When set, this bit pre- vents hardware from changing the link speed for device specific reasons other than to correct unreliable link operation by reduc- ing the link speed.
Page 115 IDT Configuration Registers Notes Field Default Type Description Field Name Value Enter Modified Compliance. When this bit is set to 1b, the port Sticky transmits the modified compliance pattern if the LTSSM enters Polling.Compliance state. This register is intended for debug, compliance testing purposes only.
Page 116: Power Management Capability Structure
IDT Configuration Registers Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. Power Management Capability Structure PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name Value CAPID Capability ID.
Page 117: Message Signaled Interrupt Capability Structure
IDT Configuration Registers Notes PMCSR - PCI Power Management Control and Status (0x0C4) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state and to set a new power state. 0x0 - (d0) D0 state 0x1 -(d1) D1 state (not supported by the PES4T4G2 and reserved)
Page 118 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 NXTPTR Next Pointer. This field contains a pointer to the next capability structure. This field is set to 0x0 indicating that it is the last capa- bility. Enable. This bit enables MSI. 0x0 - (disable) disabled 0x1 - (enable) enabled 19:17...
Page 119: Subsystem Id And Subsystem Vendor Id
IDT Configuration Registers Notes MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) Field Default Type Description Field Name Value 15:0 MDATA Message Data. This field contains the lower 16-bits of data that are written when a MSI is signalled. 31:16 Reserved Reserved.
Page 120: Advanced Error Reporting (Aer) Enhanced Capability
IDT Configuration Registers Notes ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configu- ration space register value pointed to by the ECFGADDR regis- ter.
Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value COMPTO Completion Time-out Status. A switch port does not initiate non-posted requests on its own behalf. Therefore, this field is hardwired to zero. CABORT Completer Abort Status. The PES4T4G2 never responds to a non-posted request with a completer abort.
Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value SDOENERR Surprise Down Error Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 123 IDT Configuration Registers Notes Field Default Type Description Field Name Value MAL- Malformed TLP Mask. When this bit is set, the corresponding bit FORMED Sticky in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 124 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the speci- Sticky ficiation. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding event is Sticky not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported error.
Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in the Sticky AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
Page 126 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Single Bit Error Status. When the Single Bit Error AER Reporting Sticky Enable (SBEAEREN) bit is set in the Memory Error Control (MECTL) register, this bit is set whenever a single bit error is detected in any memory associated with the port.
Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value Single Bit Error Mask. When this bit is set and the Single Bit Error Sticky AER Reporting Enable (SBEAEREN) bit is set in the Memory Error Control (MECTL) register, the corresponding bit in the AERCES register is masked.
Page 128: Device Serial Number Enhanced Capability
IDT Configuration Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 3rd doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error. AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default...
Page 129: Pci Express Virtual Channel Capability
IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capa- bility structure. 19:16 CAPVER Capability Version.
Page 130 IDT Configuration Registers Notes PVCCAP2- Port VC Capability 2 (0x208) Field Default Type Description Field Name Value VCARBCAP VC Arbitration Capability. This field indicates the type of VC arbitration that is supported by the port for the low priority VC group.
Page 131 IDT Configuration Registers Notes VCR0CAP- VC Resource 0 Capability (0x210) Field Default Type Description Field Name Value PARBC Upstream: Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Arbitration capability.
Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value LPAT Load Port Arbitration Table. This bit, when set, updates the Port Arbitration logic from the Port Arbitration Table for the VC resource. In addition, this field is only valid when the Port Arbitra- tion Table is used by the selected Port Arbitration scheme (that is indicated by a set bit in the Port Arbitration Capability field selected by Port Arbitration Select).
Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:18 Reserved Reserved field. VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the corresponding port arbitration period.
Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:16 PHASE12 Phase 12. This field contains the port ID for the corresponding port arbitration period. 23:20 PHASE13 Phase 13. This field contains the port ID for the corresponding port arbitration period.
Page 135: Power Budgeting Enhanced Capability
IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:16 PHASE28 Phase 28. This field contains the port ID for the corresponding port arbitration period. 23:20 PHASE29 Phase 29. This field contains the port ID for the corresponding port arbitration period.
Page 136: Switch Control And Status Registers
IDT Configuration Registers Notes PWRBD - Power Budgeting Data (0x288) Field Default Type Description Field Name Value 31:0 DATA Data. If the Data Value Select (DVSEL) field in the Power Bud- geting Data Select register contains a value of zero through 7, then this field returns the contents of the corresponding Power Budgeting Data Value (PWRBDVx) register.
Page 137 IDT Configuration Registers Notes Field Default Type Description Field Name Value CCLKDS HWINIT Common Clock Downstream. This bit reflects the value of the CCLKDS signal sampled during Fundamental Reset. CCLKUS HWINIT Common Clock Upstream. This bit reflects the value of the CCLKUS signal sampled during Fundamental Reset.
Page 138 IDT Configuration Registers Notes Field Default Type Description Field Name Value PWRBDVUL Power Budgeting Data Value Unlock. When this bit is set, the Sticky Power Budgeting Data Value [7:0] (PWRBDV[7:0]) registers in all ports may be read and written. When this bit is cleared, then the PWRBDV registers in all ports are read-only.
Page 139 IDT Configuration Registers Notes Field Default Type Description Field Name Value EUIDC Enable Upstream Port ID Checking. Normally TLPs with a non- Sticky zero device number that target the bus number corresponding to the upstream link and are received on a downstream port are for- warded upstream and are emitted on the upstream link.
Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value IPXILOCKP Invert Polarity of PxILOCKP. When this bit is set, the polarity of Sticky the PxILOCKP output is inverted in all ports. IPXPWRGDN Invert Polarity of PxPWRGDN. When this bit is set, the polarity Sticky of the PxPWRGDN input is inverted in all ports.
Page 141 IDT Configuration Registers Notes GPIOFUNC - General Purpose I/O Control Function (0x418) Field Default Type Description Field Name Value 15:0 GPIOFUNC GPIO Function. Each bit in this field controls the corresponding Sticky GPIO pin. When set to a one, the corresponding GPIO pin oper- ates as the alternate function as defined in Chapter 4, General Purpose I/O.
Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:9 MSMBADDR HWINIT Master SMBus Address. This field contains the SMBus address assigned to the master SMBus interface. 23:16 Reserved Reserved field. EEPROM- Serial EEPROM Initialization Done. When the switch is config- DONE ured to operate in a mode in which serial EEPROM initialization occurs during a Fundamental Reset, this bit is set when serial...
Page 143 IDT Configuration Registers Notes Field Default Type Description Field Name Value SMBDTO SMBus Disable Time-out. When this bit is set, SMBus time-outs are disabled on the master and slave SMBuses. 31:23 Reserved Reserved field. The MSMBCLK low minimum pulse width is equal to half the period programmed in this field. The value of 0x53, which corre- sponds to ~373 KHz, allows the min low pulse width to be satisfied.
Page 144 IDT Configuration Registers Notes IOEXPINTF - I/O Expander Interface (0x430) ‘ Field Default Type Description Field Name Value 15:0 IOEDATA I/O Expander Data. Each bit in this field corresponds to an I/O expander input/output signal. Reading this field returns the cur- rent value of the corresponding I/O pin state of the I/O expander number selected in the Select (SEL) field in this register (i.e., the input values last read from the I/O expander and output values...
Page 145 IDT Configuration Registers Notes IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) Field Default Type Description Field Name Value Reserved Reserved field. IOE0ADDR I/O Expander 0 Address. This field contains the SMBus address Sticky assigned to I/O expander 0 on the master SMBus interface. Reserved Reserved field.
Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value P2GPEE Port 2 General Purpose Event Enable. When this bit is set, the Sticky hot-plug INTx, MSI and PME event notification mechanisms defined by the PCIe base 2.0 specification are disabled for port 2 and are instead signalled through General Purpose Event (GPEN) signal assertions.
Page 147 IDT Configuration Registers Notes Field Default Type Description Field Name Value Low-Swing Mode Enable. When set, this bit enables Low-Swing Sticky mode operation at the SerDes Transmit logic. Please refer to section Low-Swing Transmitter Voltage Mode on page 3-8 for fur- ther details.
Page 148 IDT Configuration Registers Notes PHYLSTATE0 - Phy Link State 0 (0x540) Field Default Type Description Field Name Value LTSSMSTAT Phy LTSSM State Machine State. This field contains the current state of the Phy Link Training and Status State Machine (LTSSM). 0x0 - XMIT_EIOS 0x1 - TMOUT_1MS 0x2 - DET_QUIET...
Page 149: Autonomous Link Reliability Management
IDT Configuration Registers Notes PHYPRBS - Phy PRBS Seed (0x55C) Field Default Type Description Field Name Value 15:0 SEED 0xFFFF Phy PRBS Seed Value. This field contains the PHY PRBS Sticky seed value used for crosslink operation. When the value in this register is modified, the PRBS counter associated with this seed is reset to the seed value and re-starts counting.
Page 150 IDT Configuration Registers Notes ALRSTS - Autonomous Link Reliability Status (0x564) Field Default Type Description Field Name Value RW1C Unreliable Link Detected. This bit is set by hardware to indi- Sticky cate that the Autonomous Link Reliability logic has detected an unreliable link.
Page 151 IDT Configuration Registers Notes ALRCNT - Autonomous Link Reliability Counter (0x56C) Field Default Type Description Field Name Value ENCNT Error Number Count. This field contains the count for the num- ber of errors detected by the Autonomous Link Reliability Man- agement logic.
Page 152 IDT Configuration Registers Notes PES4T4G2 User Manual 8 - 72 May 23, 2013...
Page 153: Jtag Boundary Scan
Chapter 9 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES4T4G2: AC-coupled and DC-coupled (also called AC and DC pins).
Page 154: Table 9.1 Jtag Pin Descriptions
IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.
Page 155: Boundary Scan Chain
IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE1RN[0] PE1RP[0] PE1TN[0] PE1TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PE4RN[0] PE4RP[0] PE4TN[0] PE4TP[0] PE5RN[0] PE5RP[0] PE5TN[0] PE5TP[0] PEREFCLKN —...
Page 156: Test Data Register (Dr)
IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell SerDes Reference REFRES0 — Resistors REFRES1 — REFRES2 — REFRES3 — Table 9.2 Boundary Scan Chain (Part 2 of 2) I = Input, O = Output O = Observe, C = Control Test Data Register (DR) The Test Data register contains the following: ...
Page 157: Figure 9.4 Diagram Of Output Cell
IDT JTAG Boundary Scan Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 9.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 9.5. shift_dr EXTEST Output enable from core...
Page 158: Instruction Register (Ir)
IDT JTAG Boundary Scan Instruction Register (IR) Notes The Instruction register allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both.
Page 159: Sample/Preload
IDT JTAG Boundary Scan SAMPLE/PRELOAD Notes The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary function of SAMPLE/PRELOAD is for sampling the system state at a particular moment.
Page 160: Validate
IDT JTAG Boundary Scan VALIDATE Notes The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std. 1149.1 specification. RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
Page 161 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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